Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-04-27
2002-05-07
Meier, Stephen D. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S774000
Reexamination Certificate
active
06384449
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a nonvolatile memory, and more particularly, to a nonvolatile memory and a method for fabricating the same, which can prevent damage to a diffusion region between a selection transistor and a memory cell transistor and reduce cell size.
2. Background of Related Art
An MOS (Metal On Insulator) memory (which holds information recorded in a cell even after power is cut off) is a nonvolatile memory that has applications in fields of power-on program storage media (for example, built in a computer bios program, various equipment set-up program and the like), operation program memories for vending machine/ticketing machine, font storage media for computer/printer and etc., game machine and the like. In general, nonvolatile memories include MASK ROM, PROM, EPROM, EEPROM and flash EEPROM. An EEPROM (Electrically Erasable and Programmable Read Only Memory) will be explained as an example with respect to the related art and to the present invention.
A related art nonvolatile memory will be explained with reference to the attached drawings.
FIG. 1
illustrates a layout of the related art nonvolatile memory.
FIG. 2
illustrates a section across line I—I in FIG.
1
.
FIG. 3
illustrates a section across line II—II in FIG.
1
.
FIG. 4
illustrates a section across line III—III in FIG.
1
.
Referring to FIGS.
1
~
4
, a related art EEPROM cell is provided with a semiconductor substrate
10
having an active region and a field region. The active region has a selection transistor region ‘A’ and a cell transistor region ‘B’ defined therein. First and second gate oxide films
12
a
and
12
b
are formed in different thicknesses on the selection transistor region ‘A’ and the cell transistor region ‘B’ on the semiconductor substrate
10
, respectively. A selection gate line
13
a
is formed on a region of the second gate oxide film
12
a
in the selection transistor region ‘A’ in one direction. A floating gate pattern
13
b
and an insulating film
14
are formed on a region of the second gate oxide film
12
b
in the cell transistor region ‘B’ in a direction identical to the direction of the selection gate line
13
a
at a fixed interval. A control gate
15
a
is formed on the insulating film
14
in a direction identical to the direction of the floating gate pattern
13
b
. Impurity diffusion regions
17
of a conductivity type opposite to that of the semiconductor substrate
10
are formed in the semiconductor substrate
10
on both sides of the selection gate line
13
a
and the floating gate pattern
13
b
/the control gate line
15
a
. The impurity diffusion regions
17
are impurity regions used as source and drain regions. A bit line
20
is formed to cross the selection gate line
13
a
and the control gate line
15
a
. The unexplained reference numerals
18
and
21
are first and second interlayer insulating films,
19
is a bit line contact hole,
22
is a selection gate contact region and
23
is a common source contact region.
A related art method for fabricating the aforementioned nonvolatile memory will be explained with reference to the attached drawings.
FIGS. 5
a
~
5
g
illustrate sections across line IV—IV in
FIG. 1
for showing the steps of a related art method for fabricating a nonvolatile memory.
Referring to
FIG. 5
a
, the related art method for fabricating a nonvolatile memory starts with forming a field insulating film
11
on a field region of a semiconductor substrate
10
having a selection transistor region ‘A’, a cell transistor region ‘B’ and the field region defined thereon. Then, a first and a second gate oxide films
12
a
and
12
b
with thicknesses different from each other are formed on the selection transistor region ‘A’ and the cell transistor region ‘B’; respectively. The first gate oxide film
12
a
on the selection transistor region ‘A’ is thicker than the second gate oxide film
12
b
on the cell transistor region ‘B’. The thin second gate oxide film
12
b
on the cell transistor region ‘B’ is a tunneling oxide film. As shown in
FIG. 5
b
, a first polysilicon layer is deposited on an entire surface, and the first polysilicon layer on regions of the first and second gate oxide films
12
a
and
12
b
are selectively patterned (photolithography+etching), to form a selection gate line
13
a
on the selection transistor region ‘A’ and a floating gate pattern
13
b
on the cell transistor region ‘B’. Then, an insulating film
14
is formed on entire surfaces of the first and second gate oxide films
12
a
and
12
b
including the selection gate line
13
a
and the floating gate pattern
13
b
. The insulating film
14
has an ONO (Oxide Nitride Oxide) structure. Though not shown in the
FIGS. 5
a
-
5
g
, the floating gate pattern
13
b
, patterned in a horizontal direction, is separated in rectangular portions. As shown in
FIG. 5
c
, a second polysilicon layer
15
is formed on an entire surface of the insulating film
14
. As shown in
FIG. 5
d
, a first photoresist film PRI is coated on the second polysilicon layer
15
and subjected to selective patterning by exposure and development, to remove the first photoresist film PR
1
from upper portions of the selection transistor region ‘A’ and from a part of the cell transistor region ‘B’ adjacent to the selection transistor region ‘A’. The patterned first photoresist film PR
1
is used as a mask to remove the second polysilicon layer
15
selectively, to leave the second polysilicon layer
15
only on the insulating film
14
on the cell transistor region ‘B’. If the second polysilicon layer
15
is left only on a region on which the control gate line is to be formed for forming the control gate line (because the selection gate line
13
a
is also etched as the floating gate pattern
13
b
under the control gate line is etched), only the second polysilicon layer
15
on the selection transistor region ‘A’ is removed at first. Then, as shown in
FIG. 5
e
, the first photoresist film PR
1
is removed, and a second photoresist film PR
2
is coated on the second polysilicon layer
15
including the insulating film
14
, and subjected to patterning by exposure and development, to leave one portion of the second photoresist film PR
2
on an entire surface of the selection transistor region ‘A’ and the other portion on the second polysilicon layer
15
over the floating gate pattern
13
b
on the cell transistor region ‘B’ spaced from the one portion over the selection transistor region ‘A’. The patterned second photoresist film PR
2
is used as a mask in selectively etching and removing the second polysilicon layer
15
and portions of the floating gate pattern
13
b
, to form a control gate line
15
a
. Upon etching the second polysilicon layer
15
and the floating gate pattern
13
b
of the first polysilicon layer, the part of semiconductor substrate
10
not masked by the second photoresist film PR
2
at an interface of the selection transistor region ‘A’ and the cell transistor region ‘B’ is also etched to form a trench
16
, because of different etch selectivities and etch rates. In general, though an oxide film, a nitride film and a polysilicon layer differ in their respective etch selectivities, the etching time period must be watched carefully because an oxide film and a nitride film are etched to some extents when a polysilicon layer is etched. Under the same etch conditions, an etch rate of the nitride film is higher than the etch rate of the polysilicon layer, and an etch rate of the oxide film is higher than the etch rate of the nitride film. Because of these reasons, when the second polysilicon layer
15
and the floating gate pattern
13
b
are etched, the ONO-structured insulating film
14
, the thin second gate oxide film
12
b
, and the semiconductor substrate
10
are also etched, forming the unnecessary trench
16
. As shown in
FIG. 5
f
, the second photoresist film PR
2
is removed, and the selection gate line
13
a
and the control gate line
15
a
are used as a mask in conducting an ion injecti
Lee Ki Jik
Yu Jae Min
Hyundai Electronics Industries Co., LTD
Meier Stephen D.
LandOfFree
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