Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-06-14
2003-12-23
Fetsum, Abraham (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
Reexamination Certificate
active
06667501
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a nonvolatile memory device and a method for driving the same.
BACKGROUND ART
As one example of a nonvolatile memory device, those which use a field effect transistor including a ferroelectric film in a gate (hereinafter, referred to as a “ferroelectric FET”) have been proposed. The ferroelectric FET has a ferroelectric film and a gate electrode on a switching MOS-FET to form a nonvolatile memory device. As shown in
FIG. 6
, the ferroelectric FET is configured by successively forming an insulating film
13
, a ferroelectric film
12
and a gate electrode
14
on a substrate
8
where a source region
5
and a drain region
6
are formed.
In the above-mentioned configuration, the ferroelectric film
12
may be polarized upward or downward. Assuming that the threshold voltage of the MOS-FET can be set at either of two different values corresponding to the two polarization states, the set state can be held (stored) as long as the polarization state of the ferroelectric film
12
is held. As shown in
FIG. 7
, a word line W is connected to the gate of the transistor, a bit line B to the drain region, and a source region line S to the source region, thereby configuring a memory cell as an element at each intersection of a matrix array.
The matrix array of the conventional nonvolatile memory device composed of the above-described memory cells has a configuration as shown in
FIG. 8
, for example. In
FIG. 8
, M
11
, M
12
, M
21
and M
22
denote a transistor, respectively, which constitutes each memory cell, C
11
, C
12
, C
21
and C
22
at each intersection of the matrix array. W
1
denotes a word line connected to each gate of the transistors M
11
and M
12
. W
2
denotes a word line connected to each gate of the transistors M
21
and M
22
. S
1
denotes a source region line connected to each source region of the transistors M
11
and M
12
. S
2
denotes a source region line connected to each source region of the transistors M
21
and M
22
. B
1
denotes the bit line connected to each drain region of the transistors M
11
and M
21
. B
2
denotes a bit line connected to each drain region of the transistors M
12
and M
22
.
The logic state of a memory cell is distinguished depending upon whether the transistor M
11
, M
12
, M
21
or M
22
of the selected memory cell is in an ON or OFF state. Whether the transistor is in an ON or OFF state is determined depending upon whether a channel under the gate of the transistor is conducting or not. A gate voltage, by which the channel of the transistor is conducted when applied to the gate of the transistor, that is, a threshold voltage, can be separated corresponding to the two polarization states of the ferroelectric film. For instance, a gate and a channel can be configured so that the transistor is turned ON in one polarization state, while the transistor is turned OFF in the other polarization state when a voltage is applied to the gate. Then, a logic of the transistor in the ON state is defined as “1”, and that in the OFF state is defined as “0”, for example.
In order to find a logic held in, for example, the memory cell C
11
in
FIG. 8
, on the basis of the above definition, the following operation should be conducted. First, the bit line B
1
is discharged to a low voltage. Then, the voltage of the source region line S
1
is increased to a readout voltage. Thereafter, the intermediate voltage between the above-described two threshold voltages is applied to the word line W
1
. When the ferroelectric film of the transistor M
11
is in a low threshold voltage state (i.e., “1”), the transistor M
11
is turned ON. Consequently, an electric current flows from the source region line S
1
to the bit line B
1
, whereby the bit line B
1
is charged, and the voltage thereof is increased. On the other hand, when the ferroelectric film of the transistor M
11
is in a high threshold voltage state, (i.e., “0”), the transistor M
11
is turned OFF. Consequently, the bit line B
1
is not charged, and the voltage thereof remains low. Therefore, the logic state held in the desired memory cell can be distinguished depending upon the high or low state of the voltage of the bit line B
1
.
However, in the case where a voltage is applied to the word line W
1
or W
2
every time data are read out, the ferroelectric film of the gate in the state “0” is applied with a voltage in a direction gradually approaching the state “1”, even when the value of the voltage is intermediate between the two threshold voltages corresponding to the above-mentioned polarization states of the ferroelectric film. As a result, all the ferroelectric films connected to the word line, to which the readout voltage is applied and which are in the state “0”, gradually approach the state “1”, every time data is read out. Accordingly, it gradually becomes difficult to discriminate the state between “0” and “1”, that is, a so-called disturbance occurs.
In order to avoid such a problem, the transistor may be designed to be set in either an enhancement state or a depletion state in accordance with the polarization state of the ferroelectric film. When the respective states are brought into correspondence with the two logic values, it is not required to apply a voltage to the word line at the time of readout.
However, the depletion-type transistor is a normally-on type, that is, in the state “1”, even when the gate voltage is zero. Therefore, the following problem might arise.
When the logic held in a non-selected memory cell is “1”, a current path from the bit line to the source line is formed via the non-selected memory cell. Then, the potential of the bit line might be varied in accordance with the state of the non-selected memory cell. To avoid this, a transistor for connecting only the transistor of the selected memory cell to the bit line is required to be added to the memory cell.
Further, in order to selectively write data only onto the transistor of a randomly selected memory cell, the substrate of the ferroelectric FET of each memory cell should be separated electrically by a well at least from the substrate of the ferroelectric FET of the memory cell connected to the adjacent word line or bit line. To solve this problem, it is necessary to add a selecting transistor to the gate of the transistor.
When the ferroelectric FETs as memory cells are arranged in a matrix in accordance with the above-described measures, a configuration as shown in
FIG. 9
is obtained. According to this configuration, it is required to provide selecting transistors TP and TB between a ferroelectric FET (M) and a word line WP, and between the ferroelectric FET (M) and a bit line B, respectively. Therefore, there arises the disadvantage that the memory cell is increased in size by several times that of a memory cell having one transistor and one capacitor (1C-1Tr memory cell).
DISCLOSURE OF THE INVENTION
Therefore, with the foregoing in mind, it is an object of the present invention to provide a nonvolatile memory device that prevents data corruption and disturbance when the data is read out from a memory cell, and in which a memory cell is composed of a smaller number of elements, and a method for driving the same.
To solve the above-described problems, a nonvolatile memory device of the present invention includes a MOS transistor having a source region, a drain region and a gate electrode, a ferroelectric film formed on the source region via an insulating film, and an electrode formed on the ferroelectric film. According to this configuration, the polarization state of the ferroelectric film formed on the source region affects the quantity of flow of electrons injected to a channel in a direction from the source region to the drain region of the MOS transistor, whereby the logic state held in the memory cell can be distinguished. In this configuration, since a voltage applied to the gate electrode at the time of readout has no influence on the ferroelectric film, the data corruption and disturbance at the time of readout of data from the memory cell can be
Fetsum Abraham
Merchant & Gould P.C.
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