Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2002-12-23
2004-09-14
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185270, C365S185330, C365S218000
Reexamination Certificate
active
06791884
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a writing/erasing system suitable for use in a nonvolatile semiconductor memory device, and relates to, for example, a technology suitable for application to a nonvolatile memory device like an electrically erasable programmable read-only memory and an LSI (Large Scale Integration) like a microcomputer with the nonvolatile memory device built therein.
BACKGROUND ART
As storage elements constituting a nonvolatile semiconductor memory device (hereinafter called a “nonvolatile memory”), may be mentioned, for example, so-called MOSFETs each having a two-layer gate structure, each of which includes a floating gate formed over a channel forming region lying between drain/source regions with a gate insulating film interposed therebetween, and a control gate formed over the floating gate with an intergate insulating film interposed therebetween and stores information depending on whether electrons are accumulated in the floating gate. There are also known nonvolatile storage elements each comprising a so-called MOSFET having a MONOS structure, which has a gate electrode formed over a channel forming region with a three-layered gate insulating film made up of an oxide film, a nitride film and an oxide film being interposed therebetween and accumulates electrons or positive holes in the nitride film to thereby store information.
These nonvolatile storage elements need only a relatively low voltage for the purpose of information reading, whereas they need such a relatively high voltage as to bring about the injection of hot carriers and the occurrence of a tunnel current at the gate insulating film in order to write information and erase the information. The conventional nonvolatile memory is often configured so as to be capable of operation by a single power supply with the incorporation of a boosting circuit for generating a high voltage used for writing and erasure therein.
Meanwhile, in the nonvolatile memory wherein the MOSFETs each having the MONOS structure, for accumulating the electrons or positive holes in the nitride film to thereby store the information have heretofore been formed as storage elements, a positive voltage (Vcc) is applied to the gate of each storage element upon writing and a negative high voltage (−Vpp) is applied to a well region (back gate) thereof to accumulate electrons in the nitride film, whereas upon erasure, the negative high voltage (−Vpp) is applied to the gate and the positive voltage (Vcc) is applied to the well region to accumulate positive holes in the nitride film, thereby changing the threshold value of each storage element. Let's now pay attention to one storage element. A well region includes source and drain regions and a channel forming region and is relatively large in size, whereas a gate electrode has a size approximately equal to the channel forming region. Therefore, the erasure at which a boosted high voltage is applied to a gate electrode, i.e., a word line low in parasitic capacitance as compared with the well region, brings about a decrease in load on a boosting circuit. Thus, a voltage boosting speed at erasure rather than at writing becomes fast. Since, however, stress applied to the storage element increases as the voltage boosting speed becomes fast, a defective condition or problem arises in that the maximum number of rewritings (hereinafter called “rewrite resistance”) is limited.
The negative high voltage (−Vpp) identical to the gate electrode is applied to a well region of each non-selected or erase-free storage element upon erasure to prevent positive holes from being accumulated in a nitride film. In such a case, a problem arises in that the magnitude of a load on the boosting circuit changes according to the number of non-selected wells, and the voltage boosting speed becomes slow as the number of the non-selected wells increases, whereas the voltage boosting speed becomes fast as the number of the non-selected wells decreases, whereby rewrite resistance of the memory varies according to each system.
Namely, a memory rewritable in byte units shares the use of a well in byte units. Therefore, the number of the non-selected wells varies according to the rewrite mode, i.e., rewriting for each byte or rewriting in page units in such a memory as to be capable of being subjected to rewriting in a unit like, for example, 64 bytes that belong to the same word line, which is called a “page mode” in addition to the rewriting in the byte units. Therefore, a problem arises in that a system wherein access to the memory in the page mode in which the number of non-selected wells is small, is often made, becomes fast in terms of an average voltage boosting speed as compared with a system wherein access to the memory in the byte units is often made, so that memory's rewrite resistance is degraded.
However, the design of the conventional nonvolatile memory has placed emphasis on a rewrite time. Such design that even upon rewriting in the byte units in which the number of the non-selected wells increases, the capability of-the boosting circuit is enhanced so that the rewriting is completed within a predetermined time to thereby make the voltage boosting speed fast, has been often effected on the nonvolatile memory. Therefore, such a nonvolatile memory as to be capable of performing both simultaneous rewriting (including rewriting in page mode) of plural bytes and rewriting in byte units is accompanied by a problem that rewrite resistance is degraded as the rewriting of the plural bytes increases.
An object of the present invention is to provide a nonvolatile memory high in rewrite resistance and a semiconductor integrated circuit like, for example, a microcomputer with the nonvolatile memory built therein.
Another object of the present invention is to provide a nonvolatile memory capable of avoiding a great variation in rewrite resistance due to the way of using a system to be utilized, and a semiconductor integrated circuit like, for example, a microcomputer with the nonvolatile memory built therein.
The above, other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
DISCLOSURE OF THE INVENTION
Summaries of typical ones of the inventions disclosed in the present application will be described in brief as follows:
A voltage boosting speed of a boosting circuit is of importance upon writing and erasing in terms of an improvement in rewrite resistance of a nonvolatile memory. As the voltage boosting speed becomes slow, stress applied to each storage element is reduced and hence the rewrite resistance is enhanced. As the voltage boosting speed becomes fast, stress applied to each storage element increases and hence the rewrite resistance is degraded. It is therefore desirable that the voltage boosting speed is slow and the voltage boosting speed is constant regardless of the number of rewrite bytes. While the rewrite resistance is enhanced as the voltage boosting speed becomes slow, a time interval required for rewriting becomes long as the voltage booting speed becomes excessively slow. Therefore, the balance between the two is also of importance.
The present invention provides a nonvolatile memory in which a load on a boosting circuit changes according to the number of rewrite bytes. In the nonvolatile memory, the boosting circuit is configured so as to perform boosting at a predetermined relatively slow speed regardless of the number of rewrite bytes. More specifically, there is provided a nonvolatile memory, comprising a power terminal, a ground terminal, a plurality of nonvolatile storage elements, a control circuit, a boosting circuit for boosting a power supply voltage supplied to the power terminal, wherein a high voltage generated by the boosting circuit is applied to each of back gates of the nonvolatile storage elements to thereby perform writing or erasing, and the magnitude of a load on the boosting circuit varies upon writing and erasing of each memory
Matsuda Yuki
Oda Tadashi
Dinh Son T.
Renesas Technology Corp.
LandOfFree
Nonvolatile memory does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Nonvolatile memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Nonvolatile memory will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3195168