Static information storage and retrieval – Systems using particular element – Ferroelectric
Reexamination Certificate
2001-08-17
2003-01-14
Nelms, David (Department: 2224)
Static information storage and retrieval
Systems using particular element
Ferroelectric
C365S200000
Reexamination Certificate
active
06507509
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a non-volatile memory, and more particularly to a single electron transistor memory, which uses a ferroelectric layer for a gate portion.
BACKGROUND OF THE INVENTION
FIG. 8
shows in section the structure of a conventional single electron transistor memory. Specifically,
FIG. 8
shows one of the examples of the successful use of a single electron transistor as a non-volatile memory device, which is constructed in a manner that a floating electrode
81
is disposed on the plane of a substrate between the single electron transistor and its gate (see Appl. Phys. Lett. 71, 2038, 1997, by Chen et al., Appl. Phys. Lett. 68, 1377 (1996) by S. Tiwari et al., and Tech. Dig. Int. Electron Devices Meet., 541 (1993) by L. Guo et al.). Such a memory operates reading/writing by using the electron emission of Fowler-Nordheim type (FN). Its structure is characterized by easy storage of data even at the high temperature of the memory.
For the writing operation, first, a voltage between a source
1
and a drain
2
is et at 0, then a voltage is applied to a gate electrode
7
, and F/N electron emission is started when a predetermined voltage or higher is reached. Accordingly, a gate electric field is generated between the floating electrode
81
and an island electrode
3
, and a current between the source
1
and the drain
2
is controlled. For the reading operation, first, electrons are tunneled through insulating layers
4
and
5
when a bias voltage is applied between the source
1
and the drain
2
, and stored in the island electrode
3
. By measuring a current between the source
1
and drain
2
at this time, stored information can be read with high sensitivity, due to single electron tunneling through quantized energy levels in the island.
SUMMARY OF THE INVENTION
However, the FN electron emission needs a relatively high electric field intensity because of the tunneling of electrons through a barrier layer between the gate and the floating electrode. Consequently, power consumption is increased, and deterioration inevitably occurs because of electric field stress applied on the barrier layer, thereby putting a limit on the number of rewriting times. In addition, conventionally, a relatively large resistance component has placed a limit on a response speed (about ms). In other words, since the conventional single electron memory is operated by tunneling the electrons through the gate insulating film, it has been difficult to achieve high device reliability, reduce power consumption, attain a high operation speed, and so on.
The object of the present invention is to achieve high device reliability, reduce power consumption, and attain a high-speed operation by realizing a device operation, which prevent the tunneling phenomenon of electrons through a gate insulating film by using a ferroelectric layer for a gate portion.
More specifically, the objects of the invention are as follows.
To realize a high-speed operation at the polarization response of an atomic order, by using the polarization of the ferroelectric layer as memory writing/erasing means.
To realize an operation using a very small amount of electrons and consuming lower power, by using a single electron transistor for reading electrons.
To provide high durability (mainly decided by the durability of the ferroelectric layer) and greatly reduce a device size, by eliminating the necessity of electrons tunneling through a gate insulating film.
To facilitate and simplify a manufacturing process compared with an Si ferroelectric memory process, by using an established semiconductor manufacturing method (3-layer resist and 3-angle aluminum (Al) deposition (see Jpn. J. Appl. Phys. 35, 1465 (1996) by Y. Nakamura et al.), or the like) so as to eliminate the necessity of precise control of an insulating film (thickness/horizontal direction), preventing the quality of a deposited Al electrode from being affected from its layered surface.
To screen the increase of a gate capacity caused by a high dielectric constant of a ferroelectric film, by providing a Low-k layer (SiO
2
) as a gate layer structure.
To enhance the flatness/crystallinity of a ferroelectric layer by using ferroelectric layer growth on a lower gate metal electrode.
To prevent the thermal diffusion of a ferrorlectric component to Si in the heat treatment process of the ferroelectric layer by providing a diffusion barrier layer.
To increase the degree of device integration by employing a layered structure.
According to the invention, to achieve the above-noted objects, mainly a ferroelectric layer is used for the electron storage portion of a non-volatile memory (especially, single electron transistor memory). In the non-volatile memory, if a ferrorlectric material is used for a capacitor portion, a writing operation is carried out by a polarization switch. Accordingly, an operation speed becomes very high (several nanoseconds). Moreover, since no high electric fields are necessary for the tunneling of electrons through the barrier layer, the use of the ferroelectric material is very advantageous for reducing power consumption and enhancing durability.
In accordance with a first means for solution of the invention, a non-volatile memory is provided, comprising:
a gate;
a ferroelectric layer disposed on the gate; and
an island electrode disposed on the ferroelectric layer, held
between a source and a drain by interpolating insulating layers
between the island and each of the source and the drain, and electrically connected to the gate.
In accordance with a second means for solution of the invention, a non-volatile memory is provided, comprising:
a gate;
a ferroelectric layer disposed on the gate;
a Low-k layer disposed on the ferroelectric layer; and
an island electrode disposed on the Low-k layer, held between a source and a drain by interpolating insulating layers between the island electrode and each of the source and the drain, and electrically connected to the gate.
In accordance with a third means for solution of the invention, a non-volatile memory is provided, comprising:
a gate;
a ferroelectric layer disposed on the gate;
an upper gate disposed on the ferroelectric layer;
a Low-k layer disposed on the ferroelectric layer;
an island electrode disposed on the Low-k layer, held between a source and a drain by interpolating insulating layers between the island electrode and each of the source and the drain, and electrically connected to the gate.
REFERENCES:
patent: 5146299 (1992-09-01), Lampe et al.
patent: 5519812 (1996-05-01), Ishihara
patent: 5969380 (1999-10-01), Seyyedy
patent: 6140163 (2000-10-01), Gardner et al.
patent: 6205048 (2001-03-01), Lee
patent: 2002/0054522 (2002-05-01), Inoue et al.
patent: 8-64803 (1996-03-01), None
patent: 10-41502 (1998-02-01), None
US patent application Publication US 2002/0054522 ; Inoue et al. US class: 365/200.
Nakamura Yasunobu
Ohtsuka Youichi
Sone Jun'ichi
Tsai Jaw-Shen
Yasui Takanari
Japan Science and Technology Corporation
Nguyen Thinh
Young & Thompson
LandOfFree
Nonvolatile memory does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Nonvolatile memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Nonvolatile memory will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3050750