Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-11-20
2002-08-20
Crane, Sara (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S321000, C257S324000
Reexamination Certificate
active
06437396
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a structure and a process of a nonvolatile memory, especially to a nonvolatile memory having a high reliability and a small size.
BACKGROUND OF THE INVENTION
The applications of nonvolatile memories have become more and more popular, such as electrically erasable programmable read only memory (EEPROM) and flash memory. The nonvolatile memory can memorize a data even when the power is shut down. In the early time, there are two types of nonvolatile memories developed, the floating gate type and the charge trapping type. Both of them have two or three layers isolated layers to store electrons. Both of them have two or three layers of isolation layers to retain the charge Please refer to
FIG. 1
which is a common floating gate thin oxide memory (FLOTOX). A voltage is applied between the control gate
11
and the drain
14
to enable the oxide layer to generate the Fowler-Nordheim (F-N) tunneling effect. The electronic tunnel from the drain
14
to the floating gate
12
through the tunneling oxide
16
can increase the threshold voltage and erase data at the same time. On the other hand, the electrons in the floating gate
12
can tunnel to the drain
14
through the tunneling oxide
16
for decreasing the threshold voltage and programming data.
Please refer to
FIG. 2
which is a charge trapping type memory (or a semicondutor/oxide
itride/oxide/semiconductor memory (SONOS)). There are two oxide layers
24
,
25
and one nitride layer
23
below the gate
21
. A high voltage is applied between the gate
21
and the well
22
, the electrons are trapped by the nitride layer
23
from the well
22
for programming. On the other hand, for erasure, a high voltage is applied to the well
22
and the gate
21
is connected to ground to enable the holes to be injected into the nitride layer
23
to neutralize the electricity.
However, the whole nonvolatile memory is failed as long as any one cell in the memory is failed. That is to say, if any one cell in a memory can not attain the standard of retention time or endurance, the whole memory is failed and the data will be missed. The main reason of the failure of a memory is associated with the quality of the tunneling oxide. If the quality of the tunneling oxide is poor or there are some defects inside, the floating gate can not retain the charge, resulting in a data loss. Instead, more than one memories are used to retain an information. Please refer to
FIG. 3
showing a “Q-cell” as an example. It consists of two memory units in series. Unless both of the two memories
31
are failed, the data is still correct. However, although it can increase the precision of information, it needs a bigger cell size.
The main concern of the present invention is to provide a nonvolatile memory having a high reliability and a small size.
SUMMARY OF THE INVENTION
The first object of the present invention is to provide a nonvolatile memory which has a broad write/erase threshold voltage window.
The second object of the present invention is to extend the retention time and the endurance of a nonvolatile memory.
The third object of the present invention is to improve the reliability and reduce the size of a nonvolatile memory.
The fourth object of the present invention is to improve the anti-radiation ability of a nonvolatile memory.
The fifth object of the present invention is to provide a simple process for manufacturing a nonvolatile memory, which is similar to that of the traditional FLOTOX.
According to the present invention, the nonvolatile memory includes a substrate, a memory unit formed on the substrate, a floating gate formed on the memory unit, and a control gate formed on the floating gate.
In an embodiment of the present invention, the memory unit is a composite dielectric layer or an oxide
itride/oxide (ONO) layer. The ONO layer further includes a first oxide layer formed on said substrate, a nitride layer formed on the first oxide layer, and a second oxide layer formed on the nitride layer. The thickness of the first oxide layer, the nitride layer, and the second oxide layer are in the range of 20~60Å, 20~100Å, and 20~500Å respectively. Besides, the ONO layer can memorize a digital data by injecting electrons therein and erase the memorized data by injecting holes therein. The nonvolatile memory further includes a dielectric layer between the floating gate and the control gate. Moreover, the substrate has a drain and a source and there is a channel formed between them. The memory unit is between the floating gate and the channel.
In an embodiment of the present invention, an ONO layer is setting inside a FLOTOX memory. The threshold voltages for tunneling electrons or holes to FLOTOX and ONO layer are different and have a broad range. The ONO layer and the FLOTOX can be controlled separately by providing different voltages to achieve the purpose of multi-state memory. The ONO layer and the FLOTOX also can be program the same data to ensure the reliability with a small size.
Another object of the present inventions to provide a process for producing a nonvolatile memory. The process includes the steps of providing a substrate, forming a memory unit on the substrate, forming a floating gate on the memory unit, and forming a control gate on the floating gate.
The steps of forming the ONO layer include: (1) forming a first oxide layer on the substrate, (2) forming a nitride layer on the first oxide layer, and (3) forming a second oxide layer on the nitride layer. The process further includes a step of forming a dielectric layer before the control gate is formed. In addition, the process further includes a step of doping the substrate to form a drain and a source after the substrate is provided.
The present invention may best be understood through the following description with reference to the accompanying drawings, in which:
REFERENCES:
patent: 5122847 (1992-06-01), Kamiya et al.
patent: 5138410 (1992-08-01), Takebuchi
patent: 5838041 (1998-11-01), Sakagami et al.
patent: 5946240 (1999-08-01), Hisamune
patent: 6166410 (2000-12-01), Lin et al.
patent: 10-125811 (1998-05-01), None
Corless Peter F.
Crane Sara
Edwards & Angell LLP
Winbond Electronics Corporation
LandOfFree
Nonvolatile memory does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Nonvolatile memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Nonvolatile memory will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2929725