Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-03-19
2001-05-08
Wojciechowicz, Edward (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S316000, C257S317000, C257S318000, C257S298000, C257S320000, C257S321000
Reexamination Certificate
active
06229175
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the invention
The present invention generally relates to a nonvolatile memory and method of forming the same, and more particularly, the present invention relates to a flash memory and a method of forming the same.
This application is a counterpart of Japanese application Ser. No. 074715/1998, filed Mar. 23, 1998, the subject matter of which is incorporated herein by reference.
2. Description of the Related Art
FIG. 1
is a cross sectional view showing a conventional flash memory cell. As shown in
FIG. 1
, the conventional flash memory cell includes a stacked layer structure which comprises a control gate electrode
6
, an insulating film
5
, a floating gate electrode
4
, and a tunnel oxide film
3
on a p type semiconductor substrate
10
having an n
+
type source region
1
, an n
+
type source region
7
, an n
+
type drain region
2
, a p
+
type drain region
8
. The flash memory cell has a structure which is similar to that of an EPROM (Erasable Programmable Read Only Memory). However, in the conventional flash memory cell, the tunnel oxide film
3
, having a thickness of about 10 nm, is formed instead of a gate oxide film as in an EPROM. The n
+
type source region
7
is formed under the n
+
type source region
1
to prevent a tunnel leakage between bands. On the other hand, the p
+
type drain region
8
is formed under the n
+
type drain region
2
to achieve programming efficiency.
The program (write) operation is performed by injecting electrons from the n
+
type drain region
2
to the floating gate electrode
4
. Therefore, when predetermined voltages, for example 10V, 5V, 0V, are applied to the control gate electrode
6
, the n
+
type drain region
2
, and the n
+
type source region
1
, hot electrons occur near the n
+
type drain region
2
, and as a result the hot electrons are injected into the floating gate electrode
4
. Therefore, the memory cell becomes the condition (“0”) that a threshold voltage is a high.
On the other hand, the erase operation is performed by emitting the electrons in the floating gate electrode
4
into the n
+
type source region
1
via the tunnel oxide film
3
.
FIG. 2
is a schematic energy band diagram of a conventional flash memory cell in the erase operation. As shown in
FIG. 2
, the erase operation is performed by applying a high voltage to the tunnel oxide film
3
, emitting the electrons stored in the floating gate electrode
4
by tunneling, and forming the condition (“1”) that a threshold voltage is low. More specifically, the erase operation is performed by applying −10V and 5V to the control gate electrode
6
and the n
+
type source region
1
, respectively, while opening the n
+
type drain region
2
.
Further, the read operation is performed as follows. By respectively applying 1V, 5V and 0V to the control gate electrode
6
, the n
+
type drain region
2
, and the n
+
type source region
1
, a memory cell is selected, as a result the condition of the threshold voltage of the memory cell is detected.
The conventional flash memory has disclosed in “Semiconductor World, April 1991, pp. 94-98”.
In the conventional nonvolatile memory, it is desirable to prevent a situation in which the number of program and erasure cycles is decreased by a degradation of the tunnel oxide film.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a nonvolatile memory that can avoid the problem in which the number of program and erasure cycles is decreased as a result of degradation of the tunnel oxide film.
According to one aspect of the present invention, for achieving the above object, there is provided a nonvolatile memory having a floating gate electrode, a control gate electrode, a tunnel oxide film between the floating gate electrode and a semiconductor substrate, and a first insulating film between the control gate electrode and the floating gate electrode, comprising: a second insulating film which is sandwiched between the control gate electrode and the floating gate electrode, the second insulating film having a barrier height which is lower than a barrier height of the first insulating film.
According to another aspect of the present invention, for achieving the above object, there is provided a nonvolatile memory having a first floating gate electrode, a control gate electrode, a tunnel oxide film between the first floating gate electrode and a semiconductor substrate, and a first insulating film between the control gate electrode and the first floating gate electrode, comprising: a second floating gate electrode which is sandwiched between the control gate electrode and the first floating gate electrode; a second insulating film which is sandwiched between the control gate electrode and the second floating gate electrode; and a third insulating film which is sandwiched between the first and second floating gate electrodes; wherein the second and third insulating films have a combined thickness which is less than a thickness of the first insulating film.
According to another aspect of the present invention, for achieving the above object, there is provided a nonvolatile memory having a first floating gate electrode, a control gate electrode, a tunnel oxide film between the floating gate electrode and a semiconductor substrate, and a first insulating film between the control gate electrode and the first floating gate electrode, comprising: a second floating gate electrode which is sandwiched between the control gate electrode and the first floating gate electrode; a second insulating film which is sandwiched between the control gate electrode and the second floating gate electrode; and a multiple layer structure which is sandwiched between the first and second floating gate electrodes, the multiple layer structure comprising third and fourth insulating layers, the third and fourth insulating layers having different barrier heights, respectively.
According to another aspect of the present invention, for achieving the above object, there is provided a nonvolatile memory having a first floating gate electrode, a control gate electrode, a tunnel oxide film between the floating gate electrode and a semiconductor substrate, and a first insulating film between the control gate electrode and the first floating gate electrode, comprising: a second floating gate electrode which is sandwiched between the control gate electrode and the first floating gate electrode; a second insulating film which is sandwiched between the first and second floating gate electrodes; and a multiple layer structure which is sandwiched between the control gate electrode and the second floating gate electrode, the multiple layer structure comprising third and fourth insulating layers, the third and fourth insulating layers having different barrier heights, respectively.
According to another aspect of the present invention, for achieving the above object, there is provided a nonvolatile memory having a first floating gate electrode, a control gate electrode, a tunnel oxide film between the floating gate electrode and a semiconductor substrate, and a first insulating film between the control gate electrode and the first floating gate electrode, comprising: a second floating gate electrode which is sandwiched between the control gate electrode and the first floating gate electrode; a first multiple layer structure which is sandwiched between the first and second floating gate electrodes, the first multiple layer structure comprising second and third insulating layers, the second and third insulating layers having different barrier heights, respectively; and a second multiple layer structure which is sandwiched between the control gate electrode and the second floating gate electrode, the second multiple layer structure comprising fourth and fifth insulating layers, the fourth and fifth insulating layers having different barrier heights, respectively.
According to another aspect of the present invention
Jones Volentine, L.L.C.
OKI Electric Industry Co., Ltd.
Wojciechowicz Edward
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