Nonvolatile memories with floating gate spacers, and methods...

Details Nonvolatile memories with floating gate spacers, and methods... Nonvolatile memories with floating gate spacers, and methods...

2002-07-18

2003-05-27

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C438S257000, C438S258000, C438S259000, C438S266000, C438S267000, C438S296000, C438S315000

Reexamination Certificate

active

06570215

ABSTRACT:

BACKGROUND
The present invention relates to semiconductor technology, and more particularly to nonvolatile semiconductor memories.
FIG. 1
illustrates a cross-section of a conventional nonvolatile semiconductor memory. Active areas
120
in silicon substrate
130
are isolated from each other by field oxide regions
134
. Gate oxide
140
is grown over the active areas. A polysilicon layer
150
is deposited over the gate oxide and patterned to provide a floating gate over each active area. Insulating layer
160
(e.g. ONO, i.e. a combination of a silicon oxide layer, a silicon nitride layer, and another silicon oxide layer) is formed over the floating gates. A polysilicon layer
170
is deposited and patterned to provide the control gates. See S. Aritome et al., “A 0.67 um
2
Self-Aligned Shallow Trench Isolation Cell (SA-STI Cell) for 3V-Only 256 Mbit NAND EEPROMs”, IEEE Tech. Dig. of IEDM, 1994, pages 61-64.
Field oxide
134
is formed by a well-known LOCOS process in which the field oxide, and hence the active areas
120
, are defined by a photoresist mask separate from a mask which later defines the floating gates
150
. To accommodate a possible mask misalignment, the floating gates overlap the field oxide regions
134
. The overlapping portions (“wings”)
150
W of gates
150
undesirably increase the memory size, but they advantageously increase the capacitive coupling between the floating gates
150
and the control gate
170
.
To reduce the memory size, polysilicon layer
150
can be self-aligned to active areas
120
, as illustrated in
FIGS. 2
,
3
and described in the Aritome article cited above. Gate oxide
140
and polysilicon
150
are formed over the substrate
130
before formation of field oxide
134
. A silicon dioxide layer
210
(“cap oxide”) is formed over the polysilicon
150
. Then a mask (not shown) is formed defining the active areas
120
. Layers
210
,
150
,
140
are patterned as defined by that mask, and the exposed regions of substrate
130
are etched to form isolation trenches
220
. Then silicon dioxide
134
is deposited to fill the isolation trenches and cover the rest of the structure. Oxide
134
is etched back (FIG.
3
). Polysilicon
150
becomes exposed. Then “inter-poly” insulator
160
and control gate polysilicon
170
are deposited and patterned as in FIG.
1
.
Elimination of wings
150
W reduces the memory size but decreases the capacitive coupling between the floating and control gates. To improve the capacitive coupling, the etch of silicon dioxide
134
partially exposes sidewalls
150
SW of floating gates
150
. Polysilicon
170
comes down along the exposed sidewall portions, so the capacitive coupling is increased.
Another structure is disclosed in R. Shirota, “A Review of 256 Mbit NAND Flash Memories and NAND Flash Future Trend”, Nonvolatile Memory Workshop, Monterey, Calif., February 2000, pages 22-31. In that structure, before formation of inter-poly insulator
160
, an additional polysilicon layer is deposited, and is patterned with a separate mask, so that the structure has a floating gate consisting of two polysilicon layers. The additional polysilicon layer extends over the field oxide regions
134
.
SUMMARY
In some embodiments of the present invention, a floating gate is made from two polysilicon layers, but the second one of the two polysilicon layers is patterned without a separate mask. In some embodiments, the second layer is formed by a conformal deposition followed by a blanket anisotropic etch to provide polysilicon spacers in physical contact with the first layer.
The invention is not limited to embodiments which do not require an additional mask, or to embodiments in which the floating gate is made of two layers, or to embodiments using polysilicon. Some embodiments use LOCOS isolation technology. Other features of the invention are described below. The invention is defined by the appended claims.


REFERENCES:
patent: 6013551 (2000-01-01), Chen et al.
patent: 6130129 (2000-10-01), Chen
patent: 6200856 (2001-03-01), Chen
patent: 6261903 (2001-07-01), Chang et al.
patent: 6335243 (2002-01-01), Choi et al.
patent: 6355524 (2002-03-01), Tuan et al.
S. Aritome et al., “A 0.67um2Self-Aligned Shallow Trench Isolation Cell (SA-STI Cell) for 3V-256 Mbit NAND EEPROMs”, IEEE Tech. Dig. of IEDM, 1994, pp. 61-64.
R. Shirota, “A Review of 256Mbit NAND Flash Memories and NAND Flash Future Trend”, Nonvolatile Memory Workshop, Monterey, California, Feb. 2000, pp. 22-31.

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