Static information storage and retrieval – Systems using particular element – Ferroelectric
Reexamination Certificate
2000-10-27
2002-03-26
Nelms, David (Department: 2818)
Static information storage and retrieval
Systems using particular element
Ferroelectric
C365S149000, C365S065000
Reexamination Certificate
active
06363004
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a nonvolatile ferroelectric memory and a method for fabricating the same.
2. Background of the Related Art
Generally, a nonvolatile ferroelectric memory, i.e., a ferroelectric random access memory (FRAM) has a data processing speed equal to a dynamic random access memory (DRAM) and retains data even in power off. For this reason, the nonvolatile ferroelectric memory has received much attention as a next generation memory device.
The FRAM and DRAM are memory devices with similar structures, but the FRAM includes a ferroelectric capacitor having a high residual polarization characteristic. The residual polarization characteristic permits data to be maintained even if an electric field is removed.
FIG. 1
shows hysteresis loop of a general ferroelectric. As shown in
FIG. 1
, even if polarization induced by the electric field has the electric field removed, data is maintained at a certain amount (i.e., d and a states) without being erased due to the presence of residual polarization (or spontaneous polarization). A nonvolatile ferroelectric memory cell is used as a memory device by corresponding the d and a states to 1 and 0, respectively.
A related art nonvolatile ferroelectric memory device will now be described.
FIG. 2
shows unit cell of a related art nonvolatile ferroelectric memory.
As shown in
FIG. 2
, the related art nonvolatile ferroelectric memory includes a bitline B/L formed in one direction, a wordline W/L formed to cross the bitline, a plate line P/L spaced apart from the wordline in the same direction as the wordline, a transistor T
1
with a gate connected with the wordline and a source connected with the bitline, and a ferroelectric capacitor FC
1
. A first terminal of the ferroelectric capacitor FC
1
is connected with a drain of the transistor T
1
and second terminal is connected with the plate line P/L.
The data input/output operation of the related art nonvolatile ferroelectric memory device will now be described.
FIG. 3
a
is a timing chart illustrating the operation of the write mode of the related art nonvolatile ferroelectric memory device, and
FIG. 3
b
is a timing chart illustrating the operation of read mode thereof.
During the write mode, an externally applied chip enable signal CSBpad is activated from high state to low state. As the same time, if a write enable signal WEBpad is applied from high state to low state, the write mode starts. Subsequently, if address decoding in the write mode starts, a pulse applied to a corresponding wordline is transited from low state to high state to select a cell.
A high signal in a certain period and a low signal in a certain period are sequentially applied to a corresponding plate line in a period where the wordline is maintained at high state. To write a logic value “1” or “0” in the selected cell, a high signal or low signal synchronized with the write enable signal WEBpad is applied to a corresponding bitline.
In other words, a high signal is applied to the bitline, and if the low signal is applied to the plate line in a period where the signal applied to the wordline is high, a logic value “1” is written in the ferroelectric capacitor. A low signal is applied to the bitline, and if the signal applied to the plate line is high, a logic value “0” is written in the ferroelectric capacitor.
With reference to
FIG. 3
b,
the reading operation of data stored in a cell by the above operation of the write mode will now be described. If an externally applied chip enable signal CSBpad is activated from high state to low state, all of bitlines become equipotential to low voltage by an equalizer signal EQ before a corresponding wordline is selected.
Then, the respective bitline becomes inactive and an address is decoded. The low signal is transited to the high signal in the corresponding wordline according to the decoded address so that a corresponding cell is selected.
The high signal is applied to the plate line of the selected cell to destroy data corresponding to the logic value “1” stored in the ferroelectric memory. If the logic value “0” is stored in the ferroelectric memory, the corresponding data is not destroyed.
The destroyed data and the data that is not destroyed are output as different values by the ferroelectric hysteresis loop, so that a sensing amplifier senses the logic value “1” or “0”. In other words, if the data is destroyed, the “d” state is transited on an “f” state as shown by hysteresis loop of FIG.
1
. If the data is not destroyed, “a” state is transited to the “f” state. Thus, if the sensing amplifier is enabled after a set time has elapsed, the logic value “1” is output in case that the data is destroyed while the logic value “0” is output in case that the data is not destroyed.
As described above, after the sensing amplifier outputs data, to recover the data to the original data, the plate line becomes inactive from high state to low state at the state that the high signal is applied to the corresponding wordline.
A related art nonvolatile ferroelectric memory and a method for fabricating the nonvolatile ferroelectric memory will now be described.
FIG. 4
a
is a diagram that illustrates a layout of a related art nonvolatile ferroelectric memory.
Referring to
FIG. 4
a,
the related art nonvolatile ferroelectric memory is provided with a first active region
41
and a second active region
41
a
asymmetrically formed at fixed intervals. A first wordline W/L
1
is formed to cross the first active region
41
, and a second wordline W/L
2
is formed to cross the second active region
41
a
spaced a distance from the first wordline W/L
1
. A first bitline B/L
1
is formed in a direction to cross the first and second wordlines at one side of the first active region
41
, and a second bitline B/L
2
is formed parallel to the first bitline B/L
1
to cross the first and second wordlines at one side of the second active region
41
a.
A first ferroelectric capacitor FC
1
is formed over the first wordline W/L
1
and the second wordline W/L
2
and is connected to the first active region
41
. A second ferroelectric capacitor FC
2
is formed over the first wordline W/L
1
and is electrically connected to the second active region
41
a.
A first plate P/L
1
is formed over the first wordline W/L
1
and is electrically connected to the first ferroelectric capacitor FC
1
, and a second plate line P/L
2
is formed over the second wordline W/L
2
and is electrically connected to the second ferroelectric capacitor FC
2
.
FIG. 4
a
is a diagram that illustrates a layout of a unit cell, wherein the related art nonvolatile ferroelectric memory has the first and second ferroelectric capacitors FC
1
and FC
2
formed extending along a bitline direction, and the first plateline P/L
1
formed over the first wordline W/L
1
and the second plateline P/L
2
formed over the second wordline W/L
2
.
FIG. 4
b
is a diagram that illustrates a cross-section across line I-I′ in
FIG. 4
a.
Referring to
FIG. 4
b,
the related art nonvolatile ferroelectric memory is provided with a substrate
51
having an active region and a field region defined thereon, a first wordline
54
and a second wordline
54
a
formed over the active region and the field region with a first insulating layer
53
disposed inbetween, the first source/drain impurity regions
55
and
56
formed on both sides of the first wordline
54
. Second source/drain impurity regions (not shown) are formed on both sides of the second wordline
54
a.
A second insulating layer
57
is formed on an entire surface inclusive of the first and second wordlines
54
and
54
a
having a contact hole exposing the first drain impurity region
56
, and a first plug layer
58
a
is stuffed in the contact hole. A first metal layer
59
connects the first plug layer
58
a
and the first bitline (not shown). A third insulating layer
60
is formed on an entire surface inclusive of the first metal layer
59
having a contact hole e
Kang Hee Bok
Kim Jin Gu
Auduong Gene N.
Fleshner & Kim LLP
Hyundai Electronics Industries Co,. Ltd.
Nelms David
LandOfFree
Nonvolatile ferroelectric memory having shunt lines does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Nonvolatile ferroelectric memory having shunt lines, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Nonvolatile ferroelectric memory having shunt lines will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2839248