Static information storage and retrieval – Systems using particular element – Ferroelectric
Reexamination Certificate
2000-11-09
2001-12-25
Phan, Trong (Department: 2818)
Static information storage and retrieval
Systems using particular element
Ferroelectric
C365S117000
Reexamination Certificate
active
06333870
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a nonvolatile ferroelectric memory device and a method for driving the same.
2. Background of the Related Art
Generally, a nonvolatile ferroelectric memory, i.e., a ferroelectric random access memory (FRAM) has a data processing speed equal to a dynamic random access memory (DRAM) and retains data even in power off. For this reason, the nonvolatile ferroelectric memory has received much attention as a next generation memory device.
The FRAM and DRAM are memory devices with similar structures, but the FRAM includes a ferroelectric capacitor having a high residual polarization characteristic. The residual polarization characteristic permits data to be maintained even if an electric field is removed.
FIG. 1
shows hysteresis loop of a general ferroelectric. As shown in
FIG. 1
, even if polarization induced by the electric field has the electric field removed, data is maintained at a certain amount (i.e., d and a states) without being erased due to the presence of residual polarization (or spontaneous polarization). A nonvolatile ferroelectric memory cell is used as a memory device by corresponding the d and a states to 1 and 0, respectively.
A related art nonvolatile ferroelectric memory device will now be described.
FIG. 2
shows unit cell of a related art nonvolatile ferroelectric memory.
As shown in
FIG. 2
, the related art nonvolatile ferroelectric memory includes a bitline B/L formed in one direction, a wordline W/L formed to cross the bitline, a plate line P/L spaced apart from the wordline in the same direction as the wordline, a transistor T
1
with a gate connected with the wordline and a source connected with the bitline, and a ferroelectric capacitor FC
1
. A first terminal of the ferroelectric capacitor FC
1
is connected with a drain of the transistor T
1
and second terminal is connected with the plate line P/L.
The data input/output operation of the related art nonvolatile ferroelectric memory device will now be described.
FIG. 3
a
is a timing chart illustrating the operation of the write mode of the related art nonvolatile ferroelectric memory device, and
FIG. 3
b
is a timing chart illustrating the operation of read mode thereof.
During the write mode, an externally applied chip enable signal CSBpad is activated from high state to low state. At the same time, if a write enable signal WEBpad is applied from high state to low state, the write mode starts. Subsequently, if address decoding in the write mode starts, a pulse applied to a corresponding wordline is transited from low state to high state to select a cell.
A high signal in a certain period and a low signal in a certain period are sequentially applied to a corresponding plate line in a period where the wordline is maintained at high state. To write a logic value “1” or “0” in the selected cell, a high signal or low signal synchronized with the write enable signal WEBpad is applied to a corresponding bitline.
In other words, a high signal is applied to the bitline, and if the low signal is applied to the plate line in a period where the signal applied to the wordline is high, a logic value “1” is written in the ferroelectric capacitor. A low signal is applied to the bitline, and if the signal applied to the plate line is high, a logic value “0” is written in the ferroelectric capacitor.
The reading operation of data stored in a cell by the above operation of the write mode will now be described. If an externally applied chip enable signal CSBpad is activated from high state to low state, all of bitlines become equipotential to low voltage by an equalizer signal EQ before a corresponding wordline is selected.
Then, the respective bitline becomes inactive and an address is decoded. The low signal is transited to the high signal in the corresponding wordline according to the decoded address so that a corresponding cell is selected.
The high signal is applied to the plate line of the selected cell to destroy data corresponding to the logic value “1” stored in the ferroelectric memory. If the logic value “0” is stored in the ferroelectric memory, the corresponding data is not destroyed.
The destroyed data and the data that is not destroyed are output as different values by the ferroelectric hysteresis loop, so that a sensing amplifier senses the logic value “1” or “0”. In other words, if the data is destroyed, the “d” state is transited to an “f” state as shown in hysteresis loop of FIG.
1
. If the data is not destroyed, “a” state is transited to the “f” state. Thus, if the sensing amplifier is enabled after a set time has elapsed, the logic value “1” is output in case that the data is destroyed while the logic value “0” is output in case that the data is not destroyed.
As described above, after the sensing amplifier outputs data, to recover the data to the original data, the plate line becomes inactive from high state to low state at the state that the high signal is applied to the corresponding wordline.
However, the related art nonvolatile ferroelectric memory device and the method for driving the same has various disadvantages.
First, the nonvolatile ferroelectric memory cell requires chip active time and precharge time. Since the levels of the wordline and the plate line should be transited during the precharge time in the related art, the precharge time should be longer. The longer precharge time causes chip cycle time to be longer. This may deteriorate chip characteristics.
Furthermore, loading difference of bitlines is caused by the capacitance difference between the main cell and the reference cell. The loading difference cannot be solved in the related. This deteriorates sensing margin.
SUMMARY OF THE INVENTION
An object of the invention is to solve at least the above problems and/or disadvantages and to provide at least the advantages described hereinafter.
Another object of the present invention is to provide a nonvolatile ferroelectric memory device and a method for driving the same that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
Another object of the present invention is to provide a nonvolatile ferroelectric memory device and a method for driving the same that only varies a wordline during precharge time to shorten the precharge time and thus minimize chip cycle time, thereby improving chip characteristics.
Another object of the present invention is to provide a nonvolatile ferroelectric memory device and a method for driving the same that prevents loading difference of bitlines caused by the capacitance difference between a main cell and a reference cell from being generated, thereby improving sensing margin.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.
To achieve at least these objects and other advantages in a whole or in part and in accordance with purposes of the present invention, as embodied and broadly described, in a nonvolatile ferroelectric memory device provided with a plurality of sub cell arrays consisting of a plurality of main cells and at least one reference cell, wherein the reference cell of any one of the sub cell arrays is operated along with a main cell of a neighboring sub cell array, the nonvolatile ferroelectric memory device includes:
a switching unit controlled by a reference wordline signal, for selectively transmitting a reference voltage stored in a ferroelectric capacitor to a bitline; a level initiating unit for selectively initiating a level of an input terminal of the switching unit connected to the ferroelectric capacitor; and a plurality of ferroelectric capacitors connected to the input terminal
Hyundai Electronics Industries Co,. Ltd.
Le Thong
Morgan & Lewis & Bockius, LLP
Phan Trong
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