Static information storage and retrieval – Systems using particular element – Ferroelectric
Reexamination Certificate
2002-12-31
2004-08-24
Le, Thong Q. (Department: 2818)
Static information storage and retrieval
Systems using particular element
Ferroelectric
C365S201000, C365S189080
Reexamination Certificate
active
06781863
ABSTRACT:
BACKGROUND OF THE DISCLOSURE
1. Field of the Disclosure
The present invention relates to nonvolatile ferroelectric memory control devices, and more particularly, to a nonvolatile ferroelectric memory control device configured to control an internal memory dump when a ferroelectric memory is used for internal memory in a SOC (system on a chip) structure.
2. Description of the Related Art
Generally, a ferroelectric random access memory (hereinafter, referred to as ‘FRAM’) has attracted considerable attention as a next generation memory device because it has a data processing speed as fast as a Dynamic Random Access Memory DRAM and conserves data even after the power is turned off.
The FRAM includes capacitors similar to the DRAM, but the capacitors have a ferroelectric substance for utilizing the characteristic of a high residual polarization of the ferroelectric substance in which data is not low even after eliminating an electric field applied thereto.
FIG. 1
is a characteristic curve illustrating a, hysteresis loop of a general ferroelectric substance.
As shown in
FIG. 1
, a polarization induced by an electric field does not vanish but remains at a certain portion (‘d’ or ‘a’ state) even after the electric field is cleared due to existence of a residual (or spontaneous) polarization. These ‘d’ and ‘a’ states may be matched to binary values of ‘1’ and ‘0’ for use as a memory cell.
FIG. 2
is a structural diagram illustrating a unit cell of the FRAM device.
As shown in
FIG. 2
, the unit cell of the conventional FRAM is provided with a bitline B/L arranged in one direction and a wordline W/L arranged in another direction vertical to the bitline B/L. A plateline P/L is arranged parallel to the wordline and spaced at a predetermined interval.
The unit cell is also provided with a transistor T
1
having a gate connected to an adjacent wordline W/L and a source connected to an adjacent bitline B/L, and a ferroelectric capacitor FC
1
having a first terminal of the two terminals connected to a drain terminal of the transistor T
1
and a second terminal of the two terminals connected to the plateline P/L.
The data input/output operation of the conventional FRAM is now described referring to
FIGS. 3
a
and
3
b.
FIG. 3
a
is a timing diagram illustrating a write mode of the FRAM.
Referring to
FIG. 3
a
, when a chip enable signal CSBpad applied externally transits from a high to low level and simultaneously a write enable signal WEBpad also transits from a high to low level, the array is enabled to start a write mode. Thereafter, when an address is decoded in a write mode, a pulse applied to a corresponding wordline transits from a “low” to “high” level, thereby selecting the cell.
In the interval where the wordline WL is held at a high level, a high signal of a predetermined interval and a low signal of a predetermined signal are sequentially applied to a corresponding plateline PL. In order to write binary logic values ‘1’ or ‘0’ in the selected cell, ‘high’ or ‘low’ signals synchronized with the write enable signal WEBpad are applied to a corresponding bitline B/L.
In other words, when a high signal is applied to a bitline BL and a low signal is applied to a plateline PL, a logic value “1” is written in the ferroelectric capacitor FC
1
. When a low signal is applied to a bitline BL and a high signal is applied to a plateline PL, a logic value “0” is written in the ferroelectric capacitor FC
1
.
FIG. 3
b
is a timing diagram illustrating a read mode of the FRAM.
Referring to
FIG. 3
b
, when a chip enable signal CSBpad externally transits from a “high” to “low” level, all bitlines are equalized to a “low” level by an equalization signal before a required wordline is selected.
After each bitline is deactivated, an address is decoded to transit a signal on the required wordline from a “low” to “high” level, thereby selecting a corresponding unit cell. A “high” signal is applied to a plateline of the selected cell to destroy a data Qs corresponding to the logic value “1” stored in the FRAM.
If a logic value “0” is stored in the FRAM, its corresponding data Qns will not be destroyed. In this way, the destroyed and non-destroyed data output different values, respectively, according to the above-described hysteresis loop characteristics. As a result, a sense amplifier senses logic values “1” or “0”.
In other words, as shown in the hysteresis loop of
FIG. 1
, the state moves from the ‘d’ to ‘f’ when the data is destroyed while the state moves from ‘a’ to ‘f’ when the data is not destroyed. As a result, after the lapse of a predetermined time, the sense amplifier is enabled by the sense amplifier enable signal SEN. The sense amplifier outputs a logic value “1” when the data is destroyed, and the sense amplifier outputs a logic value “0” when the data is not destroyed.
After the sense amplifier amplifies and outputs the data, the data should be recovered into the original data. Accordingly, when a “high” signal is applied to the required wordline, the plateline is deactivated from “high” to “low”.
A conventional system on a chip ‘SOC’ structure using the above-described ferroelectric memory automatically separated the memory into an internal region and an external region.
The internal memory region using internal addresses and the external memory region using external addresses are previously set using a physical method on a SOC when address size is determined. For example, if an internal memory has the size of 4K bite, an internal memory is used in an address region of A
11
, A
10
, . . . , A
0
. An external expansion memory is automatically used in an address region having the size of more than 4 K bite.
In other words, once the address size of an internal memory in the SOC is set up, then internal and external address regions are automatically determined. As a result, data of the internal memory cannot be externally outputted via input/output ports in the external address region.
FIG. 4
is a diagram for explaining operations of data input/output port in a dump mode of a conventional SOC.
The dump mode is to sequentially output internal memory data via data input/output port to the outside. In a dump mode, an internal memory data DATA<m−1> is allotted to an internal address ADD<m>. A memory data DATA<m> of the final internal address region ADD<m> is outputted from the next address ADD<m+1>, the first external address. An internal address valid signal ADD_Valid to set a limit of internal address region is effective to the final internal address ADD<m>. Since an address, ADD<m+1> where the final internal memory data DATA<m> is outputted is the external address region ADD<m+1>, the final internal data DATA<m> is not outputted via a data input/output port.
As a result, memory data of the final internal address region in a boundary region between the internal address region and the external address region is not dumped during the internal memory dump mode.
Additionally, a logic for determining the size of memory address and for testing the memory address is realized with a metal option, which is a hardware-connection of metal layers to power lines. When the memory size is changed, a metal mask layer of SOC should be also changed. As a result, the process becomes complicated and the cost increases.
SUMMARY OF THE DISCLOSURE
Accordingly, it is an object of the present invention to make the data in the internal addresses be normally outputted via a data input/output port by allotting external memory region to internal memory region in a dump mode.
It is another object of the present invention to easily change the memory size by programming the memory site using a FRAM code cell.
REFERENCES:
patent: 5912849 (1999-06-01), Yasu et al.
Hynix Semicondutor Inc.
Jacobson & Holman PLLC
Le Thong Q.
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