Static information storage and retrieval – Systems using particular element – Ferroelectric
Reexamination Certificate
2002-12-30
2003-12-09
Nguyen, Tan (Department: 2818)
Static information storage and retrieval
Systems using particular element
Ferroelectric
C365S185080, C365S230080, C365S233500
Reexamination Certificate
active
06661698
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to nonvolatile ferroelectric memory control devices, and more specifically, to a nonvolatile ferroelectric memory control device suitable for an embedded memory when the FRAM is used as a program memory in a SOC (System on Chip) structure.
2. Description of the Prior Art
Generally, a ferroelectric randaom access memory (hereinafter, referred to as ‘FeRAM’) has attracted considerable attention as next generation memory device because it has a data processing speed as fast as a Dynamic Random Access Memory DRAM and conserves data even after the power is turned off.
The FRAM has structures similar to the DRAM, but does not have the capacitors made of a ferroelectric substance. The FRAM utilizes the characteristic of a high residual polarization of the ferroelectric substance in which data is not low even after eliminating an electric field applied thereto.
FIG. 1
is a characteristic curve illustrating a hysteresis loop of a general ferroelectric substance.
A polarization induced by an electric field does not vanish but remains at a certain portion (‘d’ or ‘a’ state) because of existence of a residual (or spontaneous) polarization even after the electric field is cleared. The FeRAM cell can be used as a memory device since the ‘d’ and ‘a’ states may be matched to binary values of ‘1’ and ‘0’, respectively.
FIG. 2
is a structural diagram illustrating a unit cell of the FRAM device.
The unit cell of the conventional FRAM is provided with a bitline BL arranged in one direction and a wordline WL arranged in another direction vertical to the bitline BL. A plateline PL is arranged parallel to the wordline WL and spaced at a predetermined interval.
The unit cell is also provided with a transistor T
1
having a gate connected to an adjacent wordline WL and a source connected to an adjacent bitline BL. And a ferroelectric capacitor FC
1
is connected between the drain terminal of the transistor T
1
and the plateline PL.
The data input/output operation of the conventional FRAM is now described referring to
FIGS. 3
a
and
3
b.
FIG. 3
a
is a timing diagram illustrating a write mode of the FRAM.
When entered into an active period, a chip enable signal CSB applied externally transits from a high to low level and simultaneously a write enable signal also transits from a high to low level, and then the array is enabled to start a write mode. Thereafter, if an address is decoded in a write mode, a wordline corresponding to the decoded address transits from a “low” to “high” level, thereby selecting the cell.
In the interval where the wordline WL is held at a high level, a high signal of a predetermined interval and a low signal of a predetermined interval are sequentially applied to a corresponding plateline PL. In order to write binary logic values ‘1’ or ‘0’ in the selected cell, ‘high’ or ‘low’ signals synchronized in the write enable signal are applied to a corresponding bitline BL. Here, a sense amplifier enable signal SEN is maintained at a high level.
In other words, when a high signal is applied to a bitline BL and a low signal is applied to a plateline PL, a logic value “1” is written as an input data DIN in the ferroelectric capacitor FC
1
. When a low signal is applied to a bitline BL and a high signal is applied to,a plateline PL, a logic value “0” is written as an input data DIN in the ferroelectric capacitor FC
1
.
FIG. 3
b
is a timing diagram illustrating a read mode of the FRAM.
When entered into an active period, a chip enable signal CSBpad externally transits from a “high” to “low” level, all bitlines are equalized to a “low” level by an equalization signal before selection of a required wordline WL.
After each bitline becomes inactive and an address is decoded. The wordline WL corresponding to the decoded address is transited from a “low” to “high” level, thereby selecting a corresponding unit cell. A “high” signal is applied to a plateline PL of the selected cell to destroy a data Qs corresponding to the logic value “1” stored in the FeRAM. If the logic value “0” is stored in the FeRAM, its corresponding data Qns will not be destroyed.
In this way, the destroyed and non-destroyed data are outputted as different values, respectively, according to the above-described hysteresis loop characteristics. As a result, a sense amplifier senses logic values “1” or “0”.
In other words, as shown in the hysteresis loop of
FIG. 1
, the state moves from the ‘d’ to ‘f’ when the data is destroyed while the state moves from ‘a’ to ‘f’ when the data is not destroyed. As a result, if the sense amplifier is enabled by the sense amplifier enable signal SEN after the lapse of a predetermined time, the sense amplifier outputs a logic value “1” as an output data DOUT in case the data is destroyed. While sense amplifier outputs a logic value “0” as an output data DOUT in case the data is not destroyed.
After the sense amplifier amplifies the data, the data should be recovered into the original data. Accordingly, the plateline PL becomes inactive from “high” to “low” at the state whereby a ‘high’ signal is applied to the required wordline WL.
However, a method for improving reliability has been required when the conventional FeRAM is used in System On a Chip SOC or a Stand Alone. Specifically, when voltages are frequently applied to the FeRAM cell, power consumption is increased and the reliability is degraded. Accordingly, the frequency of cell operations is required to decrease.
Additionally, in the conventional FeRAM, when addresses of cells are assigned, row/column addresses are allotted at random. As a result, power consumption is increased in cell operation of the FeRAM, and life of the cell is reduced due to the unnecessary operation applying stress to the cell.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to assign column addresses having high driving probability in the least significant bit area. Also, another object of the present invention is not to generate an address transition detecting signal for the column addresses after the first accessed column address when one or more of the column addresses are sequentially accessed in the same row address.
It is another object of the present invention to comprise a data register array for storing data corresponding to the previous address, so that the data stored in the register may be immediately outputted without driving a chip when the address is repeatedly accessed.
In order to achieve the above-described objects, there is a nonvolatile ferroelectric memory control device comprising: a column address latch for latching column addresses according to a chip enable signals; a column decoder for decoding the latched column addresses; a row address latch for latching row addresses according to the chip enable signals; and a chip control signal generator for outputting control signals for controlling chip operation according to address transition detecting signals generated when the latched row address is transited.
REFERENCES:
patent: 6385078 (2002-05-01), Jeon
Hynix / Semiconductor Inc.
Jacobson & Holman PLLC
Nguyen Tan
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