Static information storage and retrieval – Systems using particular element – Ferroelectric
Reexamination Certificate
2002-09-04
2004-08-10
Le, Thong Q. (Department: 2818)
Static information storage and retrieval
Systems using particular element
Ferroelectric
C365S198000, C365S196000
Reexamination Certificate
active
06775172
ABSTRACT:
This application claims the benefit of the Korean Application No. P2001-57275 filed on Sep. 17, 2001, which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a nonvolatile ferroelectronic memory, and more particularly, to a nonvolatile ferroelectric memory, and a method for driving the nonvolatile ferroelectric memory.
2. Discussion of the Related Art
The ferroelectric memory, i.e., FRAM(Ferroelectric Random Access Memory) is paid attention as a next generation memory. In general, the FRAM has a data processing speed similar to that of a DRAM(Dynamic Random Access Memory), and is capable of conserving data even if the power is turned off. Also, the FRAM is similar to the DRAM in structure and includes a capacitor of a ferroelectric material for utilizing a high residual polarization of the ferroelectric material. The residual polarization permits the conservation of data even after removal of an electric field.
FIG. 1
illustrates a conventional characteristic curve of a hysteresis loop of a general ferroelectric material.
Referring to
FIG. 1
, in general, a polarization induced by an electric field is not erased totally, but a certain amount (‘d’ or ‘a’ state) of which is remained, even if the electric field is removed due to existence of the residual polarization(or spontaneous polarization). The ‘d’ and ‘a’ states correspond to ‘1’ and ‘0’ respectively in application to a memory.
FIG. 2
illustrates a unit cell of a conventional non-volatile ferroelectric memory.
Referring to
FIG. 2
, the unit cell of the conventional non-volatile ferroelectric memory includes a bitline B/L formed in one direction, a wordline W/L formed in a perpendicular direction to the bitline, a plateline P/L formed in a parallel direction with the wordline W/L, a transistor TI having a gate connected to the wordline W/L and a drain connected to the bitline B/L, and a ferroelectric capacitor FC
1
having a first terminal connected to the drain of the transistor T1 and a second terminal connected to the plateline P/L.
The data input/output operation of the conventional nonvolatile ferroelectric memory will be explained.
FIG. 3A
is a diagram illustrating timing of a write mode operation of the conventional ferroelectric memory, and
FIG. 3B
is a diagram illustrating timing of a read mode operation of the conventional ferroelectric memory.
In the write mode operation, when an external chip enable signal CSBpad transits from “high” to “low” and, on the same time, an external write enable signal WEBpad transits from “high” to “low,” a write mode is started. When address decoding is started in the write mode, a pulse to be applied to the wordline W/L transits from ‘low’ to ‘high’ to select the unit cell. Thus, in a period during which the wordline W/L is held ‘high’, the plateline P/L has a ‘high’ signal applied thereto for one period and a ‘low’ signal applied thereto for another period in succession. In order to write a logical value ‘1’ or ‘0’ on the selected cell, a ‘high’ or ‘low’ signal synchronized to the write enable signal WEBpad is applied to the bitline B/L. That is, if a ‘high’ signal is applied to the bitline B/L, and a signal applied to the plateline P/L is ‘low’ in a period during which a signal applied to the wordline W/L is in a ‘high’ state, a logical value ‘1’ is then written on the ferroelectric capacitor FC
1
. If a ‘low’ signal is applied to the bitline B/L, and a signal applied to the plateline P/L is ‘high’, a logical value ‘0’ is then written on the ferroelectric capacitor FC
1
.
Next, the read mode operation of reading the data stored in the unit cell will be explained.
If the chip enable signal CSBpad transits from ‘high’ to ‘low’ externally, all bitlines B/L are equalized to a ‘low’ voltage by an equalizer signal before the wordline W/L is selected. Then, after the bitlines B/L are disabled, an address is decoded, and the decoded address transits the wordline W/L from ‘low’ to ‘high’, to select the unit cell. A ‘high’ signal is applied to the plateline P/L of the selected cell, to break a data Qs corresponding to a logical value ‘1’ stored in the ferroelectric memory.
If a logical value ‘0’ is in storage in the ferroelectric memory, a data corresponding to the logical value ‘0’ is not broken. The non-broken data and the broken data thus provide values different from each other according to the aforementioned hysteresis loop, such that a sense amplifier senses a logical value ‘1’ or ‘0’.
That is, in the hysteresis loop of
FIG. 1
, that the data is broken is a case where the value is changed from ‘d’ to ‘f’, and that the data is not broken is a case where the value is changed from ‘a’ to ‘f’. Therefore, if the sense amplifier is enabled after a certain time period is passed, in the case where the data is broken, the logical value ‘1’ is provided as amplified, and in the case where the data is not broken, the logical value ‘0’ is provided as amplified.
After the sense amplifier amplifies data, since an original data should be restored, the plateline P/L is disabled from ‘high’ to ‘low’ in a state a ‘high’ signal is applied to the wordline W/L.
A conventional nonvolatile ferroelectric memory cell array having sub bitlines and main bitlines will be explained.
Though not shown in the drawing, the conventional nonvolatile ferroelectric memory cell array is provided with a plurality of main bitlines crossing sub cell array blocks. The sub cell array block has sub bitline therein in correspondence to the main bitline. There is a switching device SW
1
, SW
2
, - - - , or SWn between the sub bitline and the main bitline for electrical connection.
FIG. 4
illustrates one conventional sub cell array block in detail.
Referring to
FIG. 4
, the sub cell array block has cells arranged in a plurality of rows and columns. Also, there are a plurality of wordline pairs each having a wordline WL and a plateline PL arranged, repeatedly. There are a plurality of main bitlines in a direction crossing the wordline paris WL<0>, PL<0>, - - - , WL<63>, PL<63>. The drawing shows an example in which 64 rows are provided. Each cell is arranged at every two columns in a row, and each cell is arranged at every two rows in a column. Therefore, once one of the wordlines and one of the platelines are enabled, only cells connected either to odd numbered sub bitline, or even numbered sub bitline are selected. Such a cell array is called as a folded bitline cell array, in which no cells overlap when the cell array is folded centered on the main bitline, when a unit cell is provided among the wordline WL, the plateline PL, and the sub bitline, and the switching device SW
1
, or SW
2
, - - - is provided at an end of the sub bitline for controlling connection between the sub bitline and the main bitline. The unit cell includes one transistor and one ferroelectric capacitor, wherein the transistor has a gate connected to a wordline, and the ferroelectric capacitor has one terminal connected to a drain (or source) of the transistor, and the other terminal connected to a plateline.
Structures of the ferroelectric capacitor, the sub bitline, and the main bitline in the foregoing nonvolatile ferroelectric memory cell array will be explained, briefly.
FIG. 5
illustrates a section of a structure of the unit cell in FIG.
4
.
Referring to
FIG. 5
, the unit nonvolatile ferroelectric memory cell includes a gate electrode
252
in one region of a silicon substrate
251
, a source
253
a
and a drain
253
b
in the silicon substrate
251
on both sides of the gate electrode
252
, a sub bitline
258
in one direction brought into contact through the drain
253
b
, a contact plug
256
, and a contact pad
257
. The numerals
254
and
255
denote first and second interlayer insulating films, respectively. There is a third interlayer insulating film
259
deposited on the sub bitline
258
, and a capacitor contact plug
260
in a contact hole formed through the first to third interlayer insulating films
254
,
255
, and
259
and
Kang Hee Bok
Kim Jung Hwan
Kye Hun Woo
Lee Geun Il
Park Je Hoon
Le Thong Q.
Morgan & Lewis & Bockius, LLP
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