Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2007-10-29
2009-08-11
Tran, Thien F (Department: 2895)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S317000, C257S321000
Reexamination Certificate
active
07573093
ABSTRACT:
A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.
REFERENCES:
patent: 5510730 (1996-04-01), El Gamal et al.
patent: 5587603 (1996-12-01), Kowshik
patent: 5625211 (1997-04-01), Kowshik
patent: 5640344 (1997-06-01), Pani et al.
patent: 5740106 (1998-04-01), Nazarian
patent: 5847993 (1998-12-01), Dejenfelt
patent: 6144580 (2000-11-01), Murray
patent: 6252273 (2001-06-01), Salter, III et al.
patent: 6356478 (2002-03-01), McCollum
patent: 7285818 (2007-10-01), Dhaoui et al.
patent: 7342278 (2008-03-01), Dhaoui et al.
patent: 2004/0114436 (2004-06-01), Hecht et al.
patent: 2004/0233736 (2004-11-01), Auricchio et al.
patent: 2007/0215935 (2007-09-01), Dhaoui et al.
patent: 2008/0093654 (2008-04-01), Dhaoui et al.
patent: 2000-12809 (2000-01-01), None
patent: 2006138086 (2006-12-01), None
Co-pending U.S. Appl. No. 11/927,265, filed Oct. 29, 2007 entitled Non-Volatile Two-Transistor Programmable Logic Cell and Array Layout.
Co-pending U.S. Appl. No. 11/927,282, filed Oct. 29, 2007 entitled Non-Volatile Two-Transistor Programmable Logic Cell and Array Layout.
Co-pending U.S. Appl. No. 11/303,865, filed Dec. 16, 2005 entitled Non-Volatile Two-Transistor Programmable Logic Cell and Array Layout.
Co-pending U.S. Appl. No. 11/152,019, filed Jun. 13, 2005, entitled Isolated-Nitride-Region Non-Volatile Memory Cell and Fabrication Method.
Bellippady Vidyadhara
Dhaoui Fethi
McCollum John
Plants William C.
Wang Zhigang
Actel Corporation
Lewis and Roca LLP
Tran Thien F
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