Non-volatile two-transistor programmable logic cell and...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S317000, C257S321000

Reexamination Certificate

active

07573093

ABSTRACT:
A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.

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Co-pending U.S. Appl. No. 11/927,265, filed Oct. 29, 2007 entitled Non-Volatile Two-Transistor Programmable Logic Cell and Array Layout.
Co-pending U.S. Appl. No. 11/927,282, filed Oct. 29, 2007 entitled Non-Volatile Two-Transistor Programmable Logic Cell and Array Layout.
Co-pending U.S. Appl. No. 11/303,865, filed Dec. 16, 2005 entitled Non-Volatile Two-Transistor Programmable Logic Cell and Array Layout.
Co-pending U.S. Appl. No. 11/152,019, filed Jun. 13, 2005, entitled Isolated-Nitride-Region Non-Volatile Memory Cell and Fabrication Method.

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