Non-volatile static random-access memory cell

Static information storage and retrieval – Systems using particular element – Flip-flop

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365185, 357 235, G11C 1140

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active

045272557

ABSTRACT:
A non-volatile memory cell (20) contains a pair of cross-coupled like-polarity FET's (Q1 and Q2) that serve as a volatile location (21) for storing a data bit and a like-polarity variable-threshold insulated-gate FET (Q3) that serves as a non-volatile storage location (22). The variable-threshold FET has its source coupled to the drain of one of the cross-coupled FET's, its insulated-gate electrode coupled to the drain of the other of the cross-coupled FET's, and its drain coupled to a power supply. A pair of impedance elements (R1 and R2) are coupled between the drains of the cross-coupled FET's, respectively, on one hand and the power supply on the other hand. Just before a power shutdown which causes the data bit to evaporate, the power supply is pulsed to a suitable level to cause the bit to be transferred to the non-volatile location. When power is restored to the normal level, the original data bit automatically returns to the volatile location.

REFERENCES:
patent: 4095281 (1978-06-01), Denes
patent: 4128773 (1978-12-01), Troutman et al.
patent: 4132904 (1979-01-01), Harari
patent: 4207615 (1980-06-01), Mar
patent: 4342101 (1982-07-01), Edwards
E. Harari et al., "A 256-Bit Nonvolatile Static RAM", 1978 IEEE ISSCC Dig. of Tech. Papers, Feb. 16, 1978, pp. 108-109.
J. Drori et al., "A Single 5V Supply Nonvolatile Static RAM", 1981 IEEE ISSCC Dig. of Tech. Papers, Feb. 19, 1981, pp. 148-149.

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