Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-03-19
2004-08-24
Nguyen, Viet Q. (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S298000, C348S222100, C348S294000, C348S302000, C365S110000
Reexamination Certificate
active
06781178
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATION
This invention is based on and claims priority of Japanese patent application 2001-083374, filed on Mar. 22, 2001, the whole contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention concerns a non-volatile solid state image pickup device and a driving method therefor and in particular concerns a non-volatile solid state image pickup device with a new pixel structure and a non-volatile solid state image pickup device drive method, wherein a new form of pixel signal reading operation is performed.
2. Description of the Related Art
MOS type solid state image pickup devices, CCD type solid state image pickup devices, CMOS type solid state image pickup devices, etc., are known as prior-art types of solid state image pickup devices.
FIG. 5
shows the structure of a prior-art MOS type solid state image pickup device.
Numerous pixels PX are aligned in array form on the surface of a semiconductor substrate. Each pixel PX contains a single photodiode PD, which is a photosensitive element, and a single MOS field effect transistor MOSFET for reading the charges that have accumulated in the photodiode PD. In the illustrated arrangement, the cathode of the photodiode PD comprises a charge accumulation region and is connected to the source region of the MOSFET A row selection signal line
103
is connected to the gate of the MOSFET and the drain of the MOSFET is connected to a read signal line
105
.
Row selection signal line
103
is connected to a vertical shift register VSR and receives row selection signals successively. Read signal line
105
is connected via a column selection transistor
107
to an output amplifier AMP. The control electrode of column selection transistor
107
is connected to a horizontal shift register HSR and receives column selection signals successively. A timing generator
109
supplies a timing signal to horizontal shift register HSR and vertical shift register VSR.
While a single pixel row is being selected by vertical shift register VSR, horizontal shift register HSR successively selects the respective columns and supplies the charges of the single row to output amplifier AMP.
This arrangement is similar to the arrangement of a DRAM, with which a memory cell is arranged from a single MOSFET and a single capacitor. Though this arrangement uses a MOSFET, it does not have an amplification function and is thus also called a passive sensor. The structure shown in
FIG. 5
has been manufactured normally using an n-MOS process.
When there is scattering of the electrical characteristics of the MOSFET's that carry out switching, non-uniformity of output will occur among pixels receiving the same amount of light and this will cause fixed pattern noise.
It is impossible to perform the image pickup operation of all pixels at once and when a moving subject is captured, the image will become blurred. It is also difficult to electronically clear the accumulated charges of all pixels at once.
FIG. 6
shows the structure of an interline CCD (IT-CCD), which is used most often among solid state image pickup devices.
With an IT-CCD, pixels, each comprised of a photodiode PD and a MOSFET, are aligned in array form as in the arrangement of FIG.
5
. However, with an IT-CCD, a vertical charge coupled device VCCD is disposed, in place of a read signal line, between pixel columns. A VCCD is connected at one end to a horizontal charge coupled device HCCD. The output end of the HCCD is connected to a floating diffusion amplifier FDA.
With an IT-CCD, the signal charges that have accumulated in the cathode region of the photodiode PD is transferred from the MOSFET to the VCCD, HCCD, and FDA, that is, transferred only among semiconductors. A VCCD has multiple transfer stages and can hold charges. Charges can thus be read into a VCCD from a number of pixels simultaneously. A still image that does not become blurred can thus be output.
A light shielding film is disposed above the charge transfer paths of the VCCD's and the HCCD and prevents light from entering into the charge transfer paths. A highly sensitive solid state image pickup device, which is not influenced readily by noise, is thus realized. Also, improvement of the image quality by employment of a fully depleted photodiode structure is progressing. Since the charges generated at the pixels can be moved to the VCCD simultaneously via transfer gates, a so-called full electronic shutter can be realized.
An IT-CCD requires a high voltage for driving, is high in consumption power, and is difficult to drive with a single power source. An IT-CCD is manufactured by a specialized process that differs from a general CMOS process. Since the charges that have been read out from the photodiodes PD are output via the VCCD's and the HCCD, random access is difficult.
FIG. 7
shows a CMOS type solid state image pickup device. Though the arrangement for just one pixel is shown in the Figure, the pixels PX are aligned in array form as in the arrangements of FIG.
5
and FIG.
6
.
Each pixel PX contains a photodiode PD, a source follower amplifier SFA for amplifying and reading the charges that have accumulated in the photodiode PD, and a reset transistor RT. The source follower amplifier SFA contains an amplifying transistor
121
, which receives the signal voltage at the gate, and a transfer transistor
123
.
The respective current terminals of transfer transistor
123
and reset transistor RT are connected to a power source line
117
. The other end of amplifying transistor
121
is connected to a read signal line
113
. The gate electrode of transfer transistor
123
is connected via a row selection signal line
111
to a vertical shift register VSR. The gate electrode of reset transistor RT is connected to a reset signal line
115
.
Read signal line
113
is connected via a noise canceller
131
to a column selection transistor
133
. The other end of column selection transistor
133
supplies an output signal via output amplifier AMP. The gate electrode of column selection transistor
133
is connected to a horizontal shift register HSR.
With the spread of portable information terminals, personal computer (PC) input cameras, and compact digital still (DS) cameras, solid state image pickup devices of low power consumption are required. CMOS solid state image pickup devices, which are based on a CMOS process and which, in comparison to a CCD type device, can be driven by a single power supply and at low power consumption, are thus being developed. With a CMOS arrangement, on-chip peripheral circuits can be realized readily and low power consumption can be realized.
Improvement of the characteristics and practical application of CMOS type solid state image pickup devices are thus progressing while making use of the abovementioned merits. With a CMOS type solid state image pickup device, low noise is realized by providing an amplification circuit for each pixel. Since a pixel contains an active element, the device is also called an active pixel sensor (APS). However, in addition to a photodiode, three or more transistors (MOSFET) are required per pixel.
When the number of MOSFET's per unit pixel increases, the operation margin of the photodiode part becomes stringent and high sensitivity and high number of (multiple) pixels become difficult to achieve. With a photodiode type CMOS solid state image pickup device, since ohmic contact is made between the reading circuit and the photodiode, it is difficult to make the entire charge accumulation region low in concentration and thus difficult to realize a fully depleted photodiode structure. Fixed pattern noise (FPN), which occurs in accordance to the deviation of the depletion layer capacity of the photodiodes, and reset noise, due to thermal fluctuation of the channel resistance of the reset transistors RT, thus occur in the process of resetting the photodiodes to a fixed potential.
Due to being an XY successive addressing type arrangement, the image becomes blurred when a mo
Arent & Fox PLLC
Nguyen Viet Q.
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