Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-12-30
2004-11-16
Wilczewski, Mary (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S315000, C257S316000
Reexamination Certificate
active
06818942
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
This application is based on and incorporates herein by reference Japanese Patent Applications No. 2002-11560 filed on Jan. 21, 2002 and No. 2002-333774 filed on Nov. 18, 2002.
1. Field of the Invention
The present invention relates to a non-volatile semiconductor storage device in which stored data are erasable has a conductive barrier layer that surrounds a floating gate.
2. Background of the Invention
An erasable programmable read-only memory (EPROM) is of a non-volatile semiconductor storage device whose data can be erased through ultra-violet irradiation. Some EPROMs have a single-layer gate structure and the other EPROMs have a two-layer gate structure. As shown in
FIGS. 18A and 18B
, an EPROM
101
of a single-layer gate structure has a control gate
5
and a floating gate
9
. The control gate
5
is formed of a high-concentrated N-type diffusion layer in a surface layer of a semiconductor substrate
2
. The floating gate
9
is formed of poly-silicon and others on a gate oxidation film
8
in the surface layer of a semiconductor substrate
2
. A P-type well
4
a
is formed on a P
−
-type substrate
3
. A drain region
16
and a source region
17
formed within the surface layer of the P-type well
4
a
are respectively disposed to adjoin both sides of the floating gate
9
. An interlayer isolating film
10
of BPSG or the like and a passivation film (not shown) are formed over the semiconductor substrate
2
that includes the floating gate
9
.
In the EPROM
101
, threshold voltage variation &Dgr;Vt of a data-unwritten cell transistor (unwritten transistor) has a tendency of increasing with electric current supply time (consecutive reading time) as shown in FIG.
19
. The tendency is remarkable in high temperature range exceeding 80° C. The same tendency is found in EPROMs that have different material or thickness of isolating layers such as the interlayer isolating film
10
. The EPROM having this tendency thereby is not used as storage device for consecutive reading at a high temperature due to the threshold voltage variation &Dgr;Vt of the unwritten transistor.
The reason for the transistor threshold voltage variation &Dgr;Vt is assumed as follows. Since the semiconductor substrate
2
is set to ground (GND) potential, voltage is applied to the control gate
5
and the drain region
16
during the reading. This affects the floating gate
9
, to which is thereby also applied the voltage. As shown in
FIG. 20
, electric potential contour lines (same electric potential lines) form numerous concentric arcs centering around the floating gate
9
and electric flux lines thereby arise from the floating gate
9
. Electric charge centers into the floating gate
9
from a surrounding area such as the interlayer isolating film
10
. This probably results in the threshold voltage variation &Dgr;Vt of the unwritten transistor during the consecutive reading at the high temperature.
An EPROM
102
shown in
FIGS. 21A and 21B
is adopted for preventing the electric charge from centering into the floating gate
9
. In the EPROM
102
, the floating gate
9
is covered with a metal wiring layer
30
using aluminum or others, and other structures are the same as that of the EPROM
101
. This EPROM is disclosed in U.S. Pat. No. 5,457,335 (JP-P3083547) and JP-A-H01-278781.
As shown in
FIG. 19
, the EPROM
102
has a smaller increase of the transistor threshold voltage variation &Dgr;Vt relative to the electric current supply time (consecutive reading time) than the EPROM
101
. The metal wiring layer
30
in the EPROM
102
is electrically connected with the control gate
5
(not shown), so that the metal wiring layer
30
is applied the voltage to during the reading.
As shown in
FIG. 22
, electric potential contour lines form numerous concentric arcs centering around the metal wiring layer
30
. The electric flux lines thereby arise from the metal wiring layer
30
instead of the floating gate
9
. Since the metal wiring layer
30
thus works as a barrier layer, the electric charge is assumed to be interrupted from centering into the floating gate
9
.
On the other hand, in EPROM manufacturing, a writing inspection to an entire EPROM and a retaining inspection to all written data are executed. All the data written and retained in the EPROM during the inspections are hence erased before product shipment in an erasing process which adopts ultra-violet irradiation on the floating gate
9
. However, since the floating gate
9
in the EPROM
102
is covered with the metal wiring layer
30
, the ultra-violet irradiation amount to the floating gate
9
is limited by the metal wiring layer
30
.
In
FIG. 23
showing relationship between ultra-violet irradiation time and transistor threshold voltage Vt, erasure of the data is completed when the transistor threshold voltage Vt decreases to approach a constant value. As shown in the results, the EPROM
102
requires more irradiation time for the erasure than the EPROM
101
, which problem leads to lowering productivity in the EPROM
102
manufacturing.
The above problem in the single-layer gate structured EPROM, involving longer erasure time, is also experienced in the two-layer gate structured EPROM where a floating gate is not covered by a control gate. In addition, the same problem is found in an electrically erasable and programmable read only memory (EEPROM) that has the same structure as the EPROM
102
. Since, in EEPROM manufacturing, a writing/erasing inspection and a retaining inspection to all the written data are executed, all the data written and retained in the EEPROM during the inspections must be also erased before product shipment.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a non-volatile semiconductor storage device whose structure suppresses threshold voltage variation of unwritten transistor during consecutive reading at high temperatures, without increasing ultra-violet irradiation time required for erasing stored data.
To achieve the above and other objects, a non-volatile semiconductor storage device is provided with a floating gate, an isolating layer, and a conductive layer as follows.
The isolating film is formed on the floating gate. The conductive layer is formed on the isolating film and is for suppressing variation of electric potential in the floating gate. The conductive layer is formed over an area surrounding the floating gate, with uncovering the floating gate.
The conductive layer hence does not cover the floating gate, so that ultra-violet irradiation to the floating gate is not interrupted. This results in no increase of the ultra-violet irradiation time required for erasing stored data. In addition, even when electric potential difference arises between the floating gate and an area surrounding the floating gate, the conductive layer can interrupt electric flux lines generated from the electric potential difference. This results in suppressing threshold voltage variation of unwritten transistor during consecutive reading at a high temperature.
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Yasushi Kasa etc., “A Partially Programmable ROM”, Electronic Information Communication Research Report, SDM90-10-23 (1990): p. 51-54.
Mizuno Shoji
Tai Akira
Denso Corporation
Lewis Monica
Wilczewski Mary
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