Non-volatile semiconductor storage device and non-volatile...

Details Non-volatile semiconductor storage device and non-volatile... Non-volatile semiconductor storage device and non-volatile...

2007-08-15

2011-10-04

Torres, Joseph D (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S780000

Reexamination Certificate

active

08032810

ABSTRACT:
This memory device comprises a word-line control circuit applying a read voltage and a soft-value read voltage as a word line voltage to a word line to generate soft-values. The soft-value read voltage is between an upper limit and a lower limit of each of plural threshold voltage distributions. A likelihood calculation circuit calculates a likelihood value of data stored in a memory cell based on the soft-value. An error correction circuit executes data error correction for the data read from the memory cell based on the likelihood value. A refresh control circuit controls a timing of a refresh operation for the memory cell based on the soft-value or the likelihood value.

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U.S. Appl. No. 12/622,868, filed Nov. 20, 2009, Sakurada.
U.S. Appl. No. 11/877,287, filed Oct. 23, 2007, Uchikawa, et al.

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