Non-volatile semiconductor memory with third electrode covering

Details Non-volatile semiconductor memory with third electrode covering Non-volatile semiconductor memory with third electrode covering

1993-01-04

1994-11-22

Limanek, Robert

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257326, H01L 2978

Patent

active

053671856

ABSTRACT:
A non-volatile semiconductor memory including a semiconductor substrate, drain and source regions which are provided on the surface of the semiconductor substrate and have P or N type differently from the semiconductor substrate, a floating gate (first gate electrode) for covering a portion of a channel region between the drain and source regions, the drain region being self-aligned with the floating gate, the source region being provided apart from the floating gate through an offset region in the channel region by a constant distance, whereby the drain and source regions are asymmetrical to each other through the floating gate, a control gate (second gate electrode) for controlling the surface potential of the whole channel region, and a third gate electrode provided above the control gate through an insulating film for substantially controlling the surface potential on the underside of the floating gate and in the vicinity thereof so that electrical writing and erasure can be performed, wherein the density of the offset region on the semiconductor substrate surface is made different from that of other portions on the semiconductor substrate surface so that electrons can be injected from a source.

REFERENCES:
patent: 4361847 (1982-11-01), Harari
patent: 4385308 (1983-05-01), Uchida
patent: 4620656 (1986-11-01), Kamiya et al.
patent: 4794565 (1988-12-01), Wu et al.
patent: 4853895 (1989-08-01), Mitchell et al.
patent: 5168465 (1992-12-01), Harari
patent: 5262987 (1993-11-01), Kojima

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