Non-volatile semiconductor memory with increased capacitance bet

Details Non-volatile semiconductor memory with increased capacitance bet Non-volatile semiconductor memory with increased capacitance bet

1994-02-18

1995-02-14

Limanek, Robert

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257322, H01L 2978

Patent

active

053898087

ABSTRACT:
In a semiconductor device, a first gate electrode and isolation layers are formed on a first gate insulation layer on a p-type silicon semiconductor substrate, and a second gate electrode is formed on the first gate electrode with a second gate insulation layer interposed therebetween. The first gate electrode is constituted by a first polycrystalline silicon layer, a second polycrystalline silicon layer and an etching stopper thin film interposed therebetween. The first gate electrode is formed by anisotropic-etching or selectively etching the second polycrystalline silicon layer, so that the etching stopper is maintained.

REFERENCES:
patent: 4812885 (1989-03-01), Riemenschneider
patent: 4833514 (1989-05-01), Esquivel et al.
patent: 5021848 (1991-06-01), Chiu
patent: 5268318 (1993-12-01), Harari
patent: 5268585 (1993-12-01), Yamauchi
Mitchell et al., "A New Self-Aligned Planar Array Cell For Ultra High Density Eproms", pp. 538-551, Published in 1987.

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