Non-volatile semiconductor memory with floating gate and control

Details Non-volatile semiconductor memory with floating gate and control Non-volatile semiconductor memory with floating gate and control

1997-03-24

1998-11-24

Thomas, Tom

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257324, 257314, 257323, 257321, H01L 29788, H01L 29792

Patent

active

058411623

ABSTRACT:
An oxide layer is formed with covering the surface of floating gates and the surface of a substrate. Control gates are formed on the oxide layer only at the portion aligning to the upper surface and at least a part of the side surface of the floating gate. By this, up to the portion in parallel to the substrate from the side surface portion of the floating gate, the control gate is not extended. Even when an interval between adjacent memory cells is reduced, opening dimension of the contact hole formed between the memory cells can be made greater. Contact resistance can be reduced. Also, the size of the memory cell can be made smaller to permit increasing of package density.

REFERENCES:
patent: 3984822 (1976-10-01), Simko et al.
patent: 4435790 (1984-03-01), Tickle et al.
patent: 5172200 (1992-12-01), Muragishi et al.
patent: 5545906 (1996-08-01), Ogura et al.
patent: 5691937 (1997-11-01), Ohta

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