Non-volatile semiconductor memory NAND structure with differentl

Details Non-volatile semiconductor memory NAND structure with differentl Non-volatile semiconductor memory NAND structure with differentl

1994-03-31

1995-11-07

Limanek, Robert P.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257391, 257399, 257519, H01L 2968

Patent

active

054649986

ABSTRACT:
A non-volatile semiconductor memory device includes NAND type memory cells arranged in a matrix pattern over a semiconductor substrate and channel stopper layers, provided on the substrate, for separating adjacent NAND type memory cells. Each NAND type memory cell includes memory cell transistors having drains and sources mutually connected in series, a source side select transistor connected to a source of one end transistor of the memory cell transistors, and a drain side select transistor connected to a drain of the other end transistor of the memory cell transistors. Each channel stopper layer has a first layer portion for separating the source side select transistors and a second layer portion for separating the memory cell transistors. Impurity concentration of the first layer portion is lower than that of the second layer portion.

REFERENCES:
patent: 5031011 (1991-07-01), Aritome et al.
Patent Abstracts of Japan, vol.: 16, No. 412, Aug. 31, 1992 (Re JP4137767).

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