Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2005-11-08
2005-11-08
Weiss, Howard (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S324000, C438S288000
Reexamination Certificate
active
06963102
ABSTRACT:
An enhanced non-volatile semiconductor memory has a source region and a drain region provided in a semiconductor substrate, an electric charge accumulating portion provided on a channel region between the source and drain regions and a control gate provided on said channel region and at least said source region is provided by introducing an impurity in self-alignment with a side wall provided on a side surface of said control gate, characterized in that an overlap of said drain region with said electric charge accumulating portion is set larger than an overlap of said source region with said electric charge accumulating portion, and an impurity dose quantity of said source region is larger than an impurity dose quantity of said drain region. The drain region may be formed by self alignment manner using a first side wall and the source region may be formed by self alignment manner using a second side wall formed on the first side wall.
REFERENCES:
patent: 5345104 (1994-09-01), Prall et al.
patent: 5631179 (1997-05-01), Sung et al.
patent: 5640345 (1997-06-01), Okuda et al.
patent: 5904518 (1999-05-01), Komori et al.
patent: 6130452 (2000-10-01), Lu et al.
patent: 05-343701 (1993-12-01), None
patent: 06-326322 (1994-11-01), None
patent: 07-297299 (1995-11-01), None
patent: 09-260513 (1997-10-01), None
patent: 10-065151 (1998-03-01), None
Cappelletti, P., et al., Flash Memories, 1999, Kluwer Academic Pubs., pp. 68-69.
“An EEPROM Cell with Asymetrical Sidewall to Minimize Drain Couplings”, Apr. 1993, IBM technical Disclosure Bulletin, vol. 36, No. 04, pp. 45-47.
Kume, H., et al., “A Flash-Erase EEPROM Cell with an Asymetric Source and Drain Structure”, 1987, IEDM 87, pp. 560-563.
Hogan & Hartson LLP
Kabushiki Karsha Toshiba
Weiss Howard
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