Static information storage and retrieval – Read/write circuit – Erase
Patent
1991-06-28
1994-02-15
Callahan, Timothy P.
Static information storage and retrieval
Read/write circuit
Erase
365185, 365900, G11C 700, G11C 1134
Patent
active
052873170
ABSTRACT:
The present invention is a non-volatile semiconductor memory device comprising a plurality of memory cells arranged in an array of rows and columns and including electrically erasable and programmable non-volatile memory transistors, row selector and column selector for decoding an externally inputted address signals to select memory cells in row and column directions, respectively. A rise detecting circuit detects the rise of a power supply, so that a latch of a latch circuit is released. A determination circuit determines whether or not the data subjected to erasing read from the memory cells is erased, so that if the read data is erased, the latch circuit is latched to set an erase-inhibit mode, thereby preventing over-erasing.
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patent: 5053990 (1991-10-01), Kreifels
patent: 5122985 (1992-06-01), Santin
patent: 5132935 (1992-07-01), Ashmore, Jr.
patent: 5172338 (1992-12-01), Mehrota
"A 90-ns One-Million Erase/Program Cycle 1-Mbit Flash Memory", Virgil N. Kynett et al., IEEE Journal of Solid-State Circuits, vol. 24, No. 5, Oct. 1989, pp. 1259-1264.
An In-System Reprogrammable 32KX8 CMOS Flash Memory, vol. 23, No. 5, Oct. 1988, Kynett et al.
ISSCC 89/Thursday, Feb. 16, 1989/East Grand Ball Room/12:15 p.m. "Nonvolatile Memories", Kynett et al.
Kobayashi Kazuo
Yamamoto Makoto
Callahan Timothy P.
Mitsubishi Denki & Kabushiki Kaisha
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