Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-06-11
2004-03-23
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S315000, C257S320000
Reexamination Certificate
active
06710395
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device and manufacturing method thereof. More specifically, the present invention relates to a memory structure in a non-volatile semiconductor memory device and manufacturing method thereof.
2. Description of the Background Art
FIG. 14
shows an example of a memory cell structure of a conventional non-volatile semiconductor memory device. Referring to
FIG. 14
N
+
diffusion layers
2
are formed spaced from each other at a main surface of a semiconductor substrate
1
. An access gate and a floating gate are provided partially overlapping N
+
diffusion layers
2
. The access gate is formed of a polycrystalline silicon film
18
, and the floating gate is formed of a polycrystalline silicon film
6
.
A silicon oxide film
19
is formed to cover polycrystalline silicon film
18
, and a silicon oxide film
15
is formed to cover polycrystalline silicon film
6
. On the access gate and the floating gate, a conductive film (control gate)
16
is formed, and on the conductive film
16
, a silicon oxide film
17
is formed.
The method of manufacturing the non-volatile semiconductor memory device shown in
FIG. 14
will be described with reference to
FIGS. 15
to
21
.
As shown in
FIG. 15
, on the main surface of semiconductor substrate
1
, silicon oxide film
5
is grown by thermal oxidation. Thereafter, a phosphorus doped polycrystalline silicon film
6
is grown by CVD (Chemical Vapor Deposition) method, and a silicon nitride film
7
is deposited by the CVD method.
On silicon nitride film
7
, a photoresist is applied, and the photoresist is formed to a desired pattern by photolithography. Using the resist pattern as a mask, silicon nitride film
7
is etched. Thereafter, the photoresist is removed, and as shown in
FIG. 16
, polycrystalline silicon film
6
is patterned using silicon nitride film
7
as a mask.
Thereafter, referring to
FIG. 17
, arsenic (As) is introduced obliquely to substrate
1
, and thereafter annealing is performed in a nitrogen atmosphere. Thus, N
+
diffusion layer
2
of a memory transistor is formed.
Thereafter, silicon nitride film
7
is removed by hot phosphoric acid, and the exposed portion of silicon oxide film
5
is etched by using an HF solution. At this time, silicon oxide film
5
immediately below polycrystalline silicon film
6
is left. Thereafter, as shown in
FIG. 18
, an interlayer insulating film
15
is deposited by the CVD method.
Thereafter, referring to
FIG. 19
, a phosphorus doped polycrystalline silicon film
18
is deposited by the CVD method. By etching back the phosphorus doped polycrystalline silicon film
18
, polycrystalline silicon film
18
is left between polycrystalline silicon films
6
, as shown in FIG.
20
. The polycrystalline silicon film
18
serves as an access gate.
Thereafter, as shown in
FIG. 21
, the surface of the access gate is thermally oxidized, to form a silicon oxide film
19
. Thereafter, a phosphorus doped polycrystalline silicon film is deposited by the CVD method, and thereafter a WSi film is deposited by the CVD method, to form conductive film
16
shown in FIG.
14
. On conductive film
16
, a silicon oxide film
17
is deposited by the CVD method.
By photolithography and etching, conductive film
16
and silicon oxide film
17
are patterned to form stripes. Thus, control gates are formed. Thereafter, using the patterned conductive film
16
and silicon oxide film
17
, interlayer insulating film
15
is etched. Thereafter, using the patterned interlayer insulating film
15
as a mask, polycrystalline silicon film
6
is etched to form a floating gate. Thus, a non-volatile semiconductor memory device shown in
FIG. 14
is obtained.
In the non-volatile semiconductor memory device having the above described structure, information is stored in the memory cell in accordance with whether the threshold voltage of the memory transistor is high with electrons introduced to the floating gate, or the threshold voltage of the memory transistor is low with the electrons discharged from the floating gate.
In the state where electrons are introduced to the floating gate, the threshold voltage of the memory transistor has a high value Vthp, which state is also referred to as a written state. The stored charges are retained semi-permanently as they are, and therefore, the stored information is also maintained semi-permanently.
In the state where the electrons are discharged from the floating gate, the threshold voltage of the memory transistor has a low value Vthe, which state is referred to as an erased state. By detecting these two states, the data stored in the memory cell can be read.
Now, the operation of writing data to mth memory transistor in a memory area will be described with reference to FIG.
22
.
The mth memory transistor includes a control gate, a mth floating gate, a mth access gate, a mth N
+
diffusion
2
, a m+1th N
+
diffusion layer
2
and substrate
1
.
At the time of writing, referring to
FIG. 22
, a high voltage Vp (about 12V) is applied to the control gate, and substrate
1
is grounded. A voltage of 2V is applied to the mth access gate, while 0V is applied to the m−1th and m+1th access gates. To mth N
+
diffusion layer
2
, 5V is applied, while 0V is applied to m+1th N
+
diffusion layer
2
.
Thus, hot electrons are generated in the channel of the mth memory transistor, and the electrons are introduced to the mth floating gate. As a result, the threshold voltage of the memory transistor increases.
At the time of erasure, a high voltage Ve (−20V) is applied to the control gate, and substrate
1
, N
+
diffusion layer
2
and the access gate are grounded. Thus, electrons are discharged by the tunneling phenomenon, from the floating gate to substrate
1
. As a result, the threshold voltage of the memory transistor lowers.
At the time of reading of a selected mth memory transistor, 3.3V, for example, is applied to the control gate, and 3.3V is applied to the m+1th N
+
diffusion layer
2
, so that mth N
+
diffusion layer and the substrate
1
are grounded. Here, when the values are set such that Vthp>3.3V>Vthe, no current flows between the source and the drain of the memory transistor in the written state, while a current flows therebetween in the erased state.
The above described non-volatile semiconductor memory device, however, has the following problem. The problem will be described with reference to
FIGS. 23A and 23B
. In
FIG. 23A
, reference characters A, A′, B and C represent paths of arsenic ions.
As already described, when N
+
diffusion layers
2
are formed, arsenic ions are introduced obliquely to substrate
1
. Here, referring to
FIG. 23A
, in the paths A and A′, arsenic ions directly reach substrate
1
, so that the concentration of the introduced arsenic at the surface of substrate
1
can be defined as N′ sin &thgr; ((cm
−2
).
When the introduction is along the path B, however, the arsenic ions are projected obliquely to polycrystalline silicon film
6
. Here, arsenic ion must pass through the lower corner of polycrystalline silicon film
6
to reach substrate
1
. Therefore, the amount of arsenic that reaches the substrate
1
is reduced as compared with the paths A and A′.
When the introduction is along the path C, arsenic ions introduced to substrate
1
are hindered by the silicon nitride film
7
, and therefore the amount of arsenic reaching substrate
1
is reduced as compared with the paths A and A′, as in the case of the path B.
Therefore, as represented by &agr; in
FIG. 23A
, for example, N
+
diffusion layer
2
as the arsenic introduced region is formed with a concentration gradient. In
FIG. 23B
, the ordinate represents arsenic concentration at the surface of the substrate, while the abscissa represents position at the surface of the substrate.
When annealing is performed for 30 sec. in a nitrog
Kobayashi Kiyoteru
Sakamoto Osamu
McDermott & Will & Emery
Nelms David
Nguyen Thinh T
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