Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2003-08-01
2004-10-26
Pham, Long (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S316000, C257S318000, C257S319000, C257S324000
Reexamination Certificate
active
06809373
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a semiconductor memory device and, more particularly, to a non-volatile semiconductor memory device.
BACKGROUND OF THE INVENTION
As a conventional semiconductor memory device which has a plurality of electrically erasable and programmable read only memory cells, each being capable of storing two bits of information, there is known a cell transistor as shown schematically in FIG.
23
. In a channel forming region in a substrate
11
, between diffusion regions
12
A and
12
B in the substrate
11
, there are provided an insulating film
13
and a control gate electrode
15
, on both sides of which there are provided insulating films
14
and word line electrodes
16
.
As for the memory cell of this sort, reference is made for example to
(1) A Novel 2-Bit/Cell MONOS Memory Device with a Wrapped-Control-Gate Structure That Applies Source-Side Hot Electron Injection, 2002 Symposium on VLSI Technology Digest of a Technical Papers, p206 to 207;
(2) Japanese Patent Kokai Publication JP-P2001-230332A (JP Patent Application 2000-269892);
(3) Japanese Patent Kokai Publication JP-P2002-26149A (JP Patent Application 2000-180763);
(4) Japanese Patent Kokai Publication JP-P2001-357681A (JP Patent Application 2000-180760);
(5) U.S. Pat. No. 6,399,441; and
(6) U.S. Pat. No. 6,388,293.
As another configuration of the memory cell, storing two bits of information per cell, such a structure shown in
FIG. 24
has been proposed. In the undermentioned publication (10) (Japanese Patent Kohyo Publication JP-P2001-512290A), for example, it is stated that a non-volatile memory of the MONOS (metal-ONO-silicon) structure, including, as a gate insulating film
14
, which comprises a silicon oxide film formed on a substrate, a silicone nitride film formed on the silicon oxide film and a silicon oxide film formed on the silicone nitride film, referred to as an oxide nitride oxide (ONO) film, is able to store 2-bit data per cell in a charge trapping film (silicon nitride film) sandwiched between silicon oxide films directly below the gate electrode. In an EEPROM (Electrically Erasable and Programmable Read Only Memory), having a charge trapping film and 2-bit storage node per cell, two separate bits, that is a left side node Node
1
, and a right side node Node
2
, are formed in spatially spaced apart regions in the charge trapping film. The two bits (storage nodes) are read in the opposite direction to the direction in which the bits were programmed. For example, the Node
2
is programmed in the charge trapping film in the ONO film
14
by applying a positive write voltage across the gate electrode
16
and the drain diffusion region
12
B, as the source diffusion region
12
A is grounded, for injecting sufficiently accelerated hot electrons into a region adjacent to the drain diffusion region
12
B of the charge trapping film in the ONO film
14
. The stored bits are read in the opposite direction to the direction in which the bits were written, that is by applying the positive electrode to the source electrode
16
and the source diffusion region
12
B, as the drain diffusion region
12
B is grounded. The memory cell is erased by applying a suitable erase voltage to for example the gate electrode
16
. For erasing the Node
2
, the erase voltage is applied to the drain diffusion region
12
B and, for erasing the Node
1
, the erase voltage is applied to the drain diffusion region
12
A for expelling the electrons from the charge trapping film. Thus, by applying preset gate, drain and the source voltages, two bits can be independently stored in the left and right regions of the charge trapping film directly below the gate electrode.
This sort of the memory cell has been disclosed in for example the
(7) U.S. Pat. No. 6,011,725;
(8) U.S. Pat. No. 6,256,231;
(9) Japanese Patent Kokai Publication JP-P2001-156189A (JP Patent Application 2000-306999); and
(10) Japanese Patent Kohyo Publication JP-P2001-512290A (JP Patent Application 2000-505640).
The 2-bit cell MONOS memory device, described in the above Publication (1), is now explained in detail.
In the above Publication (1), there are shown a cross-sectional view and an equivalent circuit of the MONOS memory of the one-cell two-bit configuration, shown in
FIGS. 25A
to
25
C, as well as the bias conditions for the write, erase and read operations.
The memory cell includes paired impurity diffusion regions (paired bit lines), provided in the substrate surface, plural control gates CG provided on the silicon oxide film between the neighboring diffusion regions in the substrate surface, and plural word lines WL extending in a direction perpendicular to the control gates on the ONO film on both sides of the silicon oxide film in the substrate surface, to carry out programming and erasure for the nodes by source side hot electron injection and by hot hole electron injection, respectively.
In the Publication (1), the respective storage sites below the word line WL[j] on the right hand side of the control gate CG [1+2n] are programmed in parallel. The bit line BL [I+2n−1] is set to the ground potential, the bit line BL [I+2n] is biased to 5.0V, while the word line WL[j] is biased to 9.0V. The control gate CG[I+2n] is biased to 1.0V/0.0V to induce/suppress the source side hot electron injection. The information stored on the right hand side of the control gate is erased by hot hole injection produced by the bias conditions of FIG.
25
C. During read, the bit line BL[I+2n−1] is biased to 1.5V, while the bit line BL [i+2n] is biased to 0.0V, the word line WL[j] is biased to Vread and the control gate CG [I+2n] is biased to 1.5V. For programming/erasing the storage site for the left hand side of the control gate CG [I+2n], the bias conditions for the bit line BL [I+2n−1], BL [I+2n] are exchanged. The respective bits of the memory cells are read by applying the reverse read, as indicated in FIG.
25
C.
SUMMARY OF THE DISCLOSURE
Referring to
FIG. 26
, the operation of programming in the memory cell, as disclosed in the above Publication (1), is scrutinized. The following shows the results of analyses which are based on the results of the investigations by the present inventor.
FIG. 26A
is a diagram showing the structure of a memory cell disclosed in the Publication (1).
FIG. 26A
is drawn by the present inventor for explaining the operation of memory cell disclosed in the Publication (1). In
FIG. 26A
,
201
denotes a semiconductor substrate,
202
denotes a N+ diffusion region, also simply referred to as a diffusion region,
203
denotes a gate insulating film,
204
denotes an ONO film,
205
denotes a control gate (electrode) and
206
denotes a word line (electrode). In writing (programming) in the node
1
(Node
1
), the, voltages of 5V and 0V are applied to the bit lines BL
1
and BL
2
, respectively. The voltage of 9V is applied to the word line
206
(VWL=9V). At this time, the voltage of 1V is applied to the control gate
205
(VCG=1.0V) to suppress the current flowing into the channel to a lower magnitude.
FIG. 26B
shows an electric field in a channel region in FIG.
26
A.
FIG. 26B
shows a result based on the investigation by the present inventor.
In view of the increased channel resistance, an electric field is concentrated, as shown in
FIG. 26B
, to inject the electrons into the ONO film
204
. The maximum strength point of the electric field occurs on a boundary between the word line
206
and the control gate
205
. It is at this location of the electric field concentration that the electrons migrated from the source diffusion region (BL
2
) are accelerated in the vicinity of the maximum strength of the electric field to exhibit a high energy. The accelerated electrons are sucked by the positive electric field of the word line
206
so as to be trapped in a portion of the ONO film
204
sli
NEC Electronics Corporation
Pham Long
Scully Scott Murphy & Presser
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