Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-08-19
2001-06-26
Fourson, George (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S325000
Reexamination Certificate
active
06252276
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor devices and manufacturing processes, and more particularly to methods and arrangements for introducing nitrogen into a tunnel oxide within a non-volatile memory semiconductor device.
BACKGROUND ART
A continuing trend in semiconductor technology is to build integrated circuits with more and/or faster semiconductor devices. The drive toward this ultra large-scale integration (ULSI) has resulted in continued shrinking of device and circuit features. As the devices and features shrink, new problems are discovered that require new methods of fabrication and/or new arrangements.
A flash or block erase Electrically Erasable Programmable Read Only Memory (flash EEPROM) semiconductor memory includes an array of memory cells that can be independently programmed and read. The size of each memory cell, and therefore the memory array, is made small by omitting select transistors that would enable the cells to be erased independently. The array of memory cells is typically aligned along a bit line and a word line and erased together as a block. An example of a memory of this type includes individual metal oxide semiconductor (MOS) memory cells, each of which includes a source, drain, floating gate, and control gate to which various voltages are applied to program the cell with a binary 1 or 0. Each memory cell can be read by addressing it via the appropriate word and bit lines.
An exemplary memory cell
8
is depicted in
FIG. 1
a
. As shown, memory cell
8
is viewed in a cross-section through the bit line. Memory cell
8
includes a doped substrate
12
having a top surface
11
, and within which a source
13
a
and a drain
13
b
have been formed by selectively doping regions of substrate
12
. A tunnel oxide
15
separates a floating gate
16
from substrate
12
. An interpoly dielectric
24
separates floating gate
16
from a control gate
26
. Floating gate
16
and control gate
26
are each electrically conductive and typically formed of polysilicon.
On top of control gate
26
is a silicide layer
28
, which acts to increase the electrical conductivity of control gate
26
. Silicide layer
28
is typically a tungsten silicide (e.g., WSi
2
), that is formed on top of control gate
26
prior to patterning, using conventional deposition and annealing processes.
As known to those skilled in the art, memory cell
8
can be programmed, for example, by applying an appropriate programming voltage to control gate
26
. Similarly, memory cell
8
can be erased, for example, by applying an appropriate erasure voltage to source
13
a.
When programmed, floating gate
16
will have a charge corresponding to either a binary 1 or 0. By way of example, floating gate
16
can be programmed to a binary 1 by applying a programming voltage to control gate
26
, which causes an electrical charge to build up on floating gate
16
. If floating gate
16
does not contain a threshold level of electrical charge, then floating gate
16
represents a binary 0. During erasure, the charge needs to be removed from floating gate
16
by way of an erasure voltage applied to source
13
a.
FIG. 1
b
depicts a cross-section of several adjacent memory cells from the perspective of a cross-section through the word line (i.e., from perspective A, as referenced in
FIG. 1
a
). In
FIG. 1
b,
the cross-section reveals that individual memory cells are separated by isolating regions of silicon dioxide formed on substrate
12
. For example,
FIG. 1
b
shows a portion of a floating gate
16
a
associated with a first memory cell, a floating gate
16
b
associated with a second memory cell, and a floating gate
16
c
associated with a third memory cell. Floating gate
16
a
is physically separated and electrically isolated from floating gate
16
b
by a field oxide (FOX)
14
a.
Floating gate
16
b
is separated from floating gate
16
c
by a field oxide
14
b.
Floating gates
16
a,
16
b,
and
16
c
are typically formed by selectively patterning a single conformal layer of polysilicon that was deposited over the exposed portions of substrate
12
, tunnel oxide
15
, and field oxides
14
a-b.
Interpoly dielectric layer
24
has been conformally deposited over the exposed portions of floating gates
16
a-c
and field oxides
14
a-b.
Interpoly dielectric layer
24
isolates floating gates
16
a-c
from the next conformal layer which is typically a polysilicon layer that is patterned (e.g., along the bit line) to form control gate
26
. Interpoly dielectric layer
24
typically includes a plurality of films, such as, for example, a bottom film of silicon dioxide, a middle film of silicon nitride, and a top film of silicon dioxide. This type of interpoly dielectric layer is commonly referred to as an oxide-nitride-oxide (ONO) layer. The thickness and physical properties of interpoly dielectric layer
24
affect the data retention capabilities of memory cell
8
.
The continued shrinking of the memory cells, for example, as depicted in the memory cells of
FIGS. 1
a-b,
requires that floating gates
16
a-c
be reduced in size (e.g., reduced width, length and/or height). The resulting reduced-size memory cell is typically operated with an attendant reduction in the threshold level of electrical charge that is required to program floating gate
16
to a binary 1 state. By way of example, in certain reduced-size memory cells, a binary 1 state can be represented by the electrical charge provided by as few as 5,000 electrons stored within floating gate
16
.
Consequently, there is a need to provide a thin, reliable tunnel oxide within a floating gate arrangement. One way to improve the quality of tunnel oxide
15
is to introduce nitrogen into tunnel oxide
15
. It has been found, however, that in certain fabrication processes the step of introducing nitrogen into tunnel oxide
15
can lead to reliability/fabrication problems in other devices within the integrated circuit die. Thus, there is need for improved methods and arrangements for introducing nitrogen into the tunnel oxide that avoid introduction of reliability/fabrication problems in other devices.
SUMMARY OF THE INVENTION
These needs and others are met by the present invention, which in accordance with certain aspects, provides methods and arrangements that selectively introduce nitrogen into a dielectric layer, such as, for example, a tunnel oxide in a memory cell. The improved methods and arrangements avoid introducing nitrogen into other areas/regions of the semiconductor integrated circuit die.
Thus, in accordance with certain embodiments of the present invention a method for forming a tunnel oxide in a semiconductor device is provided. The method includes forming a layer of silicon dioxide on a substrate, forming at least one additional layer on the layer of silicon dioxide, selectively patterning the at least one additional layer and the layer of silicon dioxide to form a stacked gate structure, and selectively introducing nitrogen into a portion of the substrate and an adjacent portion of the layer of silicon dioxide within the stacked gate structure. In accordance with certain embodiments of the present invention, the step of selectively introducing nitrogen into the portion of the substrate and the adjacent portion of the layer of silicon dioxide further includes the steps of implanting nitrogen into the portion of the substrate and the adjacent portion of the layer of silicon dioxide within the stacked gate structure, and causing at least a portion of the implanted nitrogen to move into the layer of silicon dioxide within the stacked gate structure by heating the stacked gate structure and the substrate.
In accordance with still other embodiments of the present invention, the step of selectively introducing nitrogen into the portion of the substrate and the adjacent portion of the layer of silicon dioxide further includes the steps of thermally diffusing nitrogen into the portion of the substrate and the adjacent portion of the layer of silicon dioxide within the stacked gate structure, and cau
Chan Vei-Han
Chang Chi
Haddad Sameer
Ramsbey Mark
Sun Yu
Advanced Micro Devices , Inc.
Fourson George
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