Non-volatile semiconductor memory device having sensitive...

Details Non-volatile semiconductor memory device having sensitive... Non-volatile semiconductor memory device having sensitive...

2001-08-20

2003-08-26

Nguyen, Van Thu (Department: 2824)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S185030, C365S185180, C365S185200, C365S185210

Reexamination Certificate

active

06611468

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device, and more specifically to a structure for reading data of a non-volatile memory cell.
2. Description of the Background Art
A conventional non-volatile semiconductor memory device basically reads data using a differential amplifier.
The structure of a sense amplifier for reading data in the conventional non-volatile semiconductor memory device will be described with reference to
FIG. 12. A
memory cell from which data is read is referred to as an array cell
6
a
, and a reference cell used for detecting data of array cell
6
a
is referred to as a reference cell
6
b.
Array cell
6
a
is connected to a current detecting portion
3
a
through Y gates (NMOS transistors)
4
a
and
5
a
, and reference cell
6
b
is connected to current detecting portion
3
a
through Y gates (NMOS transistors)
4
b
and
5
b.
Current detecting portion
3
a
, Y gates
4
a
,
5
a
and array cell
6
a
are collectively shown as a pre-sense amplifier portion
1
a
. Current detecting portion
3
b
, Y gates
4
b
,
5
b
and reference cell
6
b
are collectively shown as a pre-sense amplifier portion
1
b.
Current detecting portion
3
a
includes PMOS transistors P
1
and P
2
as well as NMOS transistors N
1
and N
2
. Transistors P
2
and N
2
are connected in series between a power supply node receiving a power supply voltage Vcc and a node GND receiving a ground voltage. Transistor P
2
has its gate receiving an enable signal E controlling activation/inactivation, whereas transistor N
2
has its gate connected to a node Z
1
.
Transistors P
1
and N
2
are connected in series between the power supply node and node Z
1
, and transistor N
1
has its gate connected to a connection node of transistors P
2
and N
2
.
When a word line VWL for driving the gate of array cell
6
a
is activated and Y gates
4
a
,
5
a
are turned on, the drain of array cell
6
a
is connected to current detecting portion
3
a
(selection of array cell
6
a
).
Current detecting portion
3
b
includes PMOS transistors P
3
and P
4
as well as NMOS transistors N
3
and N
4
. Transistors P
4
and N
4
are connected in series between the power supply node receiving the power supply voltage and node GND. Transistor P
4
has its gate receiving enable signal E, and transistor N
4
has its gate connected to a node Z
3
.
Transistors P
3
and N
3
are connected in series between the power supply node and node Z
3
, and transistor N
3
has its gate connected to the connection node of transistors P
4
and N
4
.
When word line VWL for driving the gate of reference cell
6
b
is activated and Y gates
4
b
,
5
b
are turned on, the drain of reference cell
6
b
is connected to current detecting portion
3
b.
It is noted that although the Y gates are shown as two stages of NMOS transistors, the number of stages or elements are not limited to this.
The current of array cell
6
a
detected by current detecting portion
3
a
is transferred to an NMOS diode N
5
through a PMOS transistor P
5
connected to form a current mirror
7
a
with transistor P
1
. A signal received by the gates of transistors P
1
and P
5
and a node connected to the gates are collectively indicated as Z
2
. A reference character Icell represents the detected current flowing through transistor P
5
.
The current of reference cell
6
b
detected by current detecting portion
3
b
is transferred to an NMOS diode N
6
through a PMOS transistor P
6
connected to form a current mirror
7
b
with transistor P
3
. A signal received by the gates of transistors P
3
and P
6
and a node connected to the gates are collectively indicated as Z
4
. Reference character Iref represents the detected current flowing through transistor P
6
.
Transistors P
5
and P
6
are respectively connected to NMOS diodes N
5
and N
6
at a first input node A and a second node B of a differential amplifier
2
.
Current Icell is converted to a voltage Vcell
0
by NMOS diode N
5
which is a current voltage converting element. Current Iref is converted to voltage Vref
0
by NMOS diode N
6
which is also a current voltage converting element.
It is noted that, with regard to a circuit from the current detecting portion to the current voltage converting portion, similar elements are used for both of an array cell and a reference cell.
Differential amplifier
2
includes PMOS transistors P
11
, P
12
, P
13
and NMOS transistors N
11
, N
12
, N
13
. Transistors P
11
and N
11
are connected in series between the power supply node and a node Z
5
, and transistor N
11
has its gate connected to a node A. Transistors P
12
and N
12
are connected in series between the power supply node and node Z
5
, and transistor N
12
has its gate connected to node B.
Transistor N
13
is connected between node Z
5
and node GND, and has its gate receiving a control signal IREF. Transistor P
13
is connected between a connection node of transistors P
11
, N
11
and a connection node of transistors P
12
, N
12
, and has its gate receiving a control signal IREF
2
.
Differential amplifier
2
detects a small voltage difference between nodes A and B (a difference between voltage Vcell
0
and voltage Vref
0
), and outputs the detection result from a connection node OUT of transistors P
12
and N
12
. An output circuit (not shown) converts the output from differential amplifier
2
to a signal at a logic level for output.
In a conventional sense amplifier circuit, a diode is used for the voltage converting portion in order to ultimately convert the detected current to a voltage. Hence, the voltage difference between the array cell and reference cell is not so large. Thus, differential amplifier
2
is used to detect the difference of the small voltage.
However, if a multi-level cell is used which allows a plurality of pieces of information to be stored in a single memory cell depending on a situation of a threshold value, a value of current to be detected would be even smaller. Thus, the conventional sense amplifier circuit cannot properly detect a voltage difference.
By contrast, a gain may be obtained with differential amplifiers connected in two stages to provide enhanced detection sensitivity. However, with the greater number of differential amplifiers, a delay time would be longer because of operations of the differential amplifiers in two stages. As a result, a greater amount of current would be consumed by a larger circuit.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor memory device capable of precisely reading data with a simple circuit structure.
A non-volatile semiconductor memory device according to one aspect of the present invention includes: a non-volatile memory cell; a reference cell determining stored data of the memory cell; a differential amplifier detecting a difference between voltages at first and second input nodes; a first current voltage converting element connected to the first input node for converting a first read current from the memory cell to a voltage; a second current voltage converting element connected to the second input node for converting a second read current from the reference cell to a voltage; and a gain adjusting circuit adjusting a detection sensitivity of a differential amplifier by adjusting values of the first and second read currents.
Preferably, the first and second current voltage converting elements respectively include diode elements, and the gain adjusting circuit includes a constant current circuit for supplying offset currents to the first and second input nodes.
In particular, the constant current circuit includes a first constant current circuit connected to the first input node, and a second constant current circuit connected to the second input node. The first and second constant current circuits supply substantially the same current.
Preferably, the gain adjusting circuit includes: a drive circuit generating a current with a value lower than that of the second read current based on the second read curre

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