Non-volatile semiconductor memory device having NAND structure c

Details Non-volatile semiconductor memory device having NAND structure c Non-volatile semiconductor memory device having NAND structure c

1996-11-13

1998-08-25

Crane, Sara W.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257326, 36518517, 36518531, 36518533, H01L 29788

Patent

active

057985472

ABSTRACT:
Flash EEPROM with NAND structure cells has a plurality of memory cell arrays. Each memory cell array has NAND structure of memory cell transistors arranged in column direction and connected serially. Each NAND structure cell has at its ends first and second select transistors, respectively. Control gates of corresponding cell transistors forming the NAND structure cells in respective memory cell arrays are connected together by control gate lines which are formed in row direction constituting word lines. Similarly, control gates of the first and second select transistors of respective memory cell arrays are connected respectively to first and second select gate lines parallel to the word lines. Erase control means is additionally provided to selectively supply erase control voltages, consisting of either a first voltage equal to well potential or a second voltage sufficient to cause data erasure at memory cell transistors, to those selected and unselected control gate lines, thereby to enable word line-by-line erasure of stored data.

REFERENCES:
patent: 5197027 (1993-03-01), Challa
patent: 5293337 (1994-03-01), Aritome et al.
Masuoka et al; "New Ultra High Density Eprom and Flash Eeprom With Nand Structure Cell"; 1987; pp. 552-555; IEEE.

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