Non-volatile semiconductor memory device having memory cell...

Details Non-volatile semiconductor memory device having memory cell... Non-volatile semiconductor memory device having memory cell...

2001-08-10

2004-08-31

Fahmy, Wael (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S324000, C257S751000, C257S760000, C257S315000

Reexamination Certificate

active

06784503

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-245029, filed Aug. 11, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device, and particularly to a non-volatile semiconductor memory device having a memory cell array suitable for high density and high integration.
2. Description of the Related Art
A flash memory is well known as a non-volatile semiconductor memory device, which enables electric re-writing of data and is suitable for high density and large capacity. Generally, in a flash memory, a plurality of memory cells each having a MOS transistor structure with a stacked gate in which a charge storage layer and a control gate are layered are provided in a matrix. A word-line signal is inputted to the control gates of these memory cells, and a bit-line signal is inputted to sources or drains of the memory cells.
FIG. 1A
is a plan view showing the structure of the memory cell array in a NOR-type flash memory.
FIG. 1B
is a cross-sectional view cut along the line
1
B—
1
B of the memory cell array shown in FIG.
1
A.
As shown in
FIG. 1B
, a charge storage layer
103
is formed on a p-type silicon semiconductor substrate
101
with a tunnel gate insulating film
102
inserted therebetween. A control gate
105
is formed on the charge storage layer
103
with an inter-gate insulating film
104
inserted therebetween. Each memory cell has a stacked gate in which the charge storage layer
103
and the control gate
105
are layered. This stacked gate is processed vertically in a self-aligning manner such that side end parts thereof are aligned.
Also, the memory cells each have a source region
106
A and a drain region
106
B which are formed of an n-type diffusion layer. The source region
106
A and the drain region
106
B are formed in the semiconductor substrate
101
at both sides of the stacked gate. One of the source region
106
A and the drain region
106
B is connected to a bit line
108
through a bit-line contact material
107
, and the other is connected to a common source line
110
through a common source line contact material
109
.
A structure interposing a contact material like the bit line, a structure directly connected through a buried metal line, a structure in which sources of memory cells of each bit line are connected with use of a diffusion layer, or the like is widely used to connect the common source line
110
and the source region
106
A to each other. The case of connection to the common source line
110
through the contact material
109
is now shown.
The bit-line contact material
107
described above has a side end part adjacent to a stacked gate and is constructed in a so-called self-aligned contact structure in which a part of the contact material
107
extends over the stacked gate, at its connecting part to a bit line
108
. This structure is adopted to eliminate a dimensional margin between the bit-line contact material
107
and the stacked gate, so that the memory cell array can be downsized.
To attain the self-aligned contact structure, the stacked gate is covered with a cap material
111
, e.g., a silicon nitride film. In particular, the cap material
111
is formed thick on the control gate
105
. In this manner, the contact material
107
buried in a contact hole and the control gate
105
are prevented from being short-circuited. A conductive material such as low-resistance poly-silicon or metal material is used for the contact material
107
. Note that the reference
112
denotes an inter-layer insulating film made of a BPSG film or the like.
The common source-line contact material
109
is not constructed in a self-aligned contact structure but a special margin is maintained between the stacked gate and the contact material
109
. This is because a potential difference of about 10 V occurs in a NOR-type memory when erasure operation is carried out. Since the withstanding voltage at this time is maintained, it is difficult to make a self-aligned contact.
FIG. 2A
is a plan view showing the structure of a memory cell array in a NAND-type flash memory.
FIG. 2B
is a cross-sectional view of the memory cell array shown in
FIG. 2A
, cut along the line
2
B—
2
B.
A plurality of memory cells are connected in series, with sources and drains shared between each other, thereby to construct a NAND column. At both ends of the NAND column, selection transistors are provided. Of the selection transistors provided at both ends, a drain or source of one selection transistor is connected to a bit line
208
through a bit-line contact material
207
. A drain or source of the other selection transistor is connected to a common source line
210
through a common source line contact material
209
.
The memory cells and selection transistors have stacked gates in which charge storage layer
203
and the control gate
205
are layered, like the NOR-type memory cell. The charge storage layer
203
of the selection transistor or the charge storage layer
203
and the control gate
205
are connected to the gate signal line at another portion than the region shown in the figure.
The bit-line contact material
207
has a side end part adjacent to a stacked gate and is constructed in a so-called self-aligned contact structure in which a part of the contact material
207
extends over the stacked gate, at its connecting part to a bit line
208
. This structure is adopted to eliminate a dimensional margin between the bit-line contact material
207
and the stacked gate, so that the memory cell array can be downsized. To attain the self-aligned contact structure, the stacked gate is covered with a cap material
211
, e.g., a silicon nitride film. In particular, the cap material
211
on the control gate
205
is formed thick on the control gate
205
. In this manner, the contact material
207
buried in a contact hole and the control gate
205
are prevented from being short-circuited. A conductive material such as low-resistance poly-silicon or metal material is used for the contact material
207
.
Like the bit line contact material
207
, the common source line contact material
209
is also constructed in a self-aligned contact structure, in the NAND type memory. This is because only a small potential difference (about 3 V) exists between the common source line
210
and the control gate
205
of the selection transistor adjacent to the source line in the NAND type memory, so there will not appear a problem of dielectric breakdown even if a self-aligned contact is made.
The self-aligned contact structure is adopted to reduce the dimensional margin between the contact material and the gate, thereby to shorten the cell array length in the direction of the bit-line
208
. The method of using the self-aligned contact structure to shorten the cell array length is very effective regardless of whether the memory cell is of the NAND type or NOR type.
In accordance with reduction of the design rule, the self-aligned contact structure is considered to have much higher effectiveness as the gate length is shortened. This is because it is difficult to scale variants and the like at the time of lithography, at the same ratio as that of the reduction of the gate length. Therefore, the distance between the contact material and the gate is not reduced to the level as that of the gate length.
Formation of the bit line contact material
207
and the common source line contact material
209
is normally performed as follows. At first, a stacked gate is buried by an inter-layer insulating film
213
such as a BPSG film or the like. Flattening processing is carried out by CMP or the like. The BPSG film is a film which attains an improved melting property by mixing impurities such as boron, phosphors, and the like into a silicon dioxide film.
Thereafter, contact holes are opened by dry etching. When these contact holes are ope

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