Non-volatile semiconductor memory device having EEPROM cell, dum

Details Non-volatile semiconductor memory device having EEPROM cell, dum Non-volatile semiconductor memory device having EEPROM cell, dum

1991-04-24

1994-04-12

Mottola, Steven

Static information storage and retrieval

Read/write circuit

Differential sensing

36518907, G11C 700

Patent

active

053031970

ABSTRACT:
A non-volatile semiconductor memory device comprises an EEPROM cell, a dummy cell, and a sense circuit. The EEPROM cell, the dummy cell and the sense circuit are operatively connected to a drain column line and a control column line, and the sense circuit reads out the content written in the EEPROM cell by the difference between a current flowing through the EEPROM cell from the drain column line and a current flowing through the dummy cell from the control column line. Consequently, write/erase operations of data for each one bit can be carried out in one operation, and access time can be shortened and deterioration of a cell transistor can be decreased in a read-out operation.

REFERENCES:
patent: 4642673 (1987-02-01), Miyamoto et al.
patent: 4807003 (1989-02-01), Mohammadi et al.
patent: 4935790 (1990-06-01), Cappelletti et al.
patent: 5081610 (1992-01-01), Olivo et al.
J. Miyamoto et al. "An Experimental 5-V-Only 256-kbit CMOS EEPROM with a High-Performance Single-Polysilicon Cell", IEEE J. Solid-State Circuit, vol. 21, No. 5, pp. 852-860, Oct. 1986.
H. Ishihara et al. "A Single-Polysilicon Flip-Flop EEPROM for ASIC Application", IEEE pp. 3-31.1-3.4, 1989.
Cuppens et al., "An EEPROM for Microprocessors and Custom Logic", IEEE Journal of Solid-State Circuits, vol. SC-20, No. 2, Apr. 1985, pp. 603-608.
Gastaldi et al., "A 1-Bit CMOS EEPROM with Enhanced Verification", IEEE Journal of Solid-State Circuits, vol. 23, No. 5, Oct. 1988, pp. 1150-1156.

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