Non-volatile semiconductor memory device having a memory cell gr

Details Non-volatile semiconductor memory device having a memory cell gr Non-volatile semiconductor memory device having a memory cell gr

1995-02-14

1996-06-04

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Bad bit

36518509, 365218, 371 102, G11C 700

Patent

active

055239765

ABSTRACT:
A plurality of semiconductor memory cells are arranged in the form of a matrix and capable of electrically erasing and re-programming. Each of word lines is provided commonly to the memory cells in each row of the matrix and commonly connected to the gates of these memory cells, and each of bit lines is provided commonly to the memory cells in each column of the matrix and commonly connected to the drains of these memory cells. Each of common source lines is commonly connected to the sources of the memory cells in each pair of adjacent rows of the matrix. A memory cell group in a predetermined row or row pair of the matrix is operative as a redundant memory cell group for replacement of the other group.

REFERENCES:
patent: 5033024 (1991-07-01), O'Connell et al.
patent: 5185718 (1993-02-01), Rinerson et al.
patent: 5195057 (1993-03-01), Kasa et al.
patent: 5422843 (1995-06-01), Yamada
patent: 5426608 (1995-06-01), Hagashitani

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