Non-volatile semiconductor memory device for selectively...

Details Non-volatile semiconductor memory device for selectively... Non-volatile semiconductor memory device for selectively...

2005-01-11

2005-01-11

Phan, Trong (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185190, C365S185290, C365S185300

Reexamination Certificate

active

06842376

ABSTRACT:
A method for settling threshold voltages of word lines on a predetermined level in an erasing processing of a non-volatile semiconductor memory device so as to speed up the erasing processing. A word latch circuit is provided for each word line and the threshold voltage of each memory cell is managed for each word line in a selected memory block. Each word latch circuit is shared by a plurality of word lines so as to reduce the required chip area. A rewriting voltage is set for each finished non-volatile memory and the voltage information is stored in the boot area of the non-volatile memory, so that the voltage is recognized by the system each time the system is powered.

REFERENCES:
patent: 5642309 (1997-06-01), Kim et al.
patent: 5991201 (1999-11-01), Kuo et al.
patent: 6014330 (2000-01-01), Endoh et al.
patent: 6381178 (2002-04-01), Kodama
patent: 8-96591 (1995-09-01), None
patent: 10-228784 (1997-02-01), None

Affiliated with

Also associated with

Rating

Non-volatile semiconductor memory device for selectively... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Non-volatile semiconductor memory device for selectively..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Non-volatile semiconductor memory device for selectively... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3381617