Non-volatile semiconductor memory device configured to minimize

Details Non-volatile semiconductor memory device configured to minimize Non-volatile semiconductor memory device configured to minimize

1996-02-26

1997-10-14

Dinh, Son T.

Static information storage and retrieval

Floating gate

Particular biasing

36518511, 36518529, 365218, G11C 700

Patent

active

056778759

ABSTRACT:
A non-volatile semiconductor memory device is provided in which a variation of threshold voltages of non-written memory cells and a potential variation of a selected bit line in preventing generation of drain disturb phenomenon are minimized Source lines SL.sub.1 ', SL.sub.2 ', SL.sub.3 ' and SL.sub.4 ' are provided in parallel to word lines WL.sub.1, WL.sub.2, WL.sub.3 and WL.sub.4, respectively, and selectively. When a data is to be written in a memory cell C.sub.11, a potential of a selected word line WL.sub.1 is set to a high voltage V.sub.pp, potentials of non-selected word lines WL.sub.2, WL.sub.3 and WL.sub.4 are set to the drain disturb preventing voltage, for example, an intermediate voltage V.sub.pp /2 which is a half of the high voltage. Further, a potential of a selected bit line BL.sub.1 is set to a potential V.sub.dd which is lower than the high voltage V.sub.pp, non-selected bit lines BL.sub.2, BL.sub.3 and BL.sub.4 are made open. Further, a potential of a selected source line SL.sub.1 ' is set to the ground potential GND and the non-selected source lines SL.sub.2 ', SL.sub.3 ' and SL.sub.4 ' are made open.

REFERENCES:
patent: 4958317 (1990-09-01), Terada
patent: 5274588 (1993-12-01), Manzur et al.
patent: 5379255 (1995-01-01), Shah
patent: 5384742 (1995-01-01), Miyakawa et al.

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