Non-volatile semiconductor memory device capable of...

Details Non-volatile semiconductor memory device capable of... Non-volatile semiconductor memory device capable of...

2001-12-04

2004-04-06

Yoha, Connie C. (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185170, C365S185250

Reexamination Certificate

active

06717861

ABSTRACT:

This application relies for priority upon Korean Patent Application No. 2000-076375, filed on Dec. 14, 2000, the contents of which are herein incorporated by reference in their entirety.
FIELD OF THE INVENTION
The present invention generally relates to semiconductor memory devices, and more specifically to a non-volatile semiconductor memory device capable of preventing program disturb due to a noise voltage induced at a string select line and a program method thereof.
BACKGROUND OF THE INVENTION
Demand for semiconductor memory devices capable of electrically erasable and programmable without a refresh function to retain data stored therein is on the rise. Further, attempts for improving the storage capacitance and integration of the memory device are increasing. A non-volatile memory device offers the large-scaled storage capacitance and high integration, without refresh of such a stored data, and one example of the device is a NAND-type flash memory device. Since the NAND-type flash memory device retains the data even in a case of power-off, it is widely used in applications where the possibility of power supply interruption is present such as a portable terminal equipment, a portable computer, and etc.
Conventional non-volatile semiconductor memory devices like the NAND-type flash memory device include a type of electrically erasable and programmable read-only memory (EEPROM) device typically referred to as “a flash EEPROM device”. Flash EEPROM devices generally include a semiconductor substrate (or bulk) of a first conductivity type, e.g. P-type; spaced source and drain regions of a second conductivity type, e.g. N-type, in the substrate; a channel region at a face of the substrate, between the spaced source and drain regions; a floating gate for storing charge carriers when the device is programmed; and a control gate which overlies the floating gate, opposite the channel region.
An array in the well-known NAND-type flash memory device is shown in FIG.
1
. Referring to
FIG. 1
, the memory cell array includes a plurality of cell strings
10
corresponding to bit lines. Here, two bit lines BL
0
and BL
1
and two cell strings
10
corresponding thereto are exemplified in
FIG. 1
, for the sake of convenience. Each of the cell strings
10
is composed of a string select transistor SST as a first select transistor, a ground select transistor GST as a second select transistor, and a plurality of EEPROM cells MC
0
through MC
15
being serially connected between the select transistors SST and GST. The string select transistor SST has a drain connected to a corresponding bit line and a gate connected to string select line SSL. The ground select transistor GST has a source connected to a common source line CSL and a gate connected to a ground select line GSL. Between the source of the string select transistor SST and the drain of the ground select transistor GST, the flash EEPROM cells MC
15
~MC
0
are serially connected, which are respectively connected to word lines WL
15
~WL
0
corresponding thereto.
Initially, the flash EEPROM cells in the memory cell array are erased to a certain threshold voltage, e.g. −3V. For the purpose of programming the flash EEPROM cells, a high voltage, e.g. 20V, is applied to a word line of a select memory cell for a predetermined time. Thus, the select memory cell is charged to a higher threshold voltage while the threshold voltages of unselect EEPROM cells remain unchanged.
A problem arises when it is desired to program a selected flash EEPROM cell along a word line without programming unselect memory cells on the same word line. When a program voltage is applied to the word line, the voltage is applied not only to the selected flash EEPROM cell but also to the unselected flash EEPROM cells along the same word line for programming. Thus, the unselected flash EEPROM cell, in particular the flash EEPROM cell adjacent to the selected cell, is programmed. The unintentional programming of an unselected cell connected to a selected word line is referred to herein as “program disturb.”
One of the ways for preventing program disturb is a program inhibit method employing a self-boosting scheme. The program inhibit method employing the self-boosting scheme is disclosed in U.S. Pat. No. 5,677,873 entitled “Method of Programming Flash EEPROM Integrated Circuit Memory Devices to Prevent Inadvertent Programming of Nondesignated NAND memory cells therein”, and U.S. Pat. No. 5,991,202 entitled “Method for Reducing Program Disturb during Self-Boosting in a NAND flash Memory”, which are incorporated herein by reference.
FIG. 2
is a timing diagram showing a programming operation according to the program inhibit method employing the self-boosting scheme. A ground path is blocked by applying 0V to the gate of the ground select transistor GST. A zero voltage (0V) potential is applied to a selected bit line, e.g., BL
0
, and a power supply voltage Vcc as the program inhibit voltage such as 3.3 V or 5V is applied to an unselected bit line, e.g., BL
1
. At the same time, the power supply voltage Vcc is applied to the gate of the string select transistor SST connected to the bit line BL
1
, which causes the source of the string select transistor SST (or the channel of a program inhibited cell transistor) to be charged up to Vcc-Vth (Vth is a threshold voltage of the string select transistor). Here, the string select transistor SST is substantially blocked or shut off. A time period for the aforementioned operation is referred to “a bit line setup period”.
Next, the channel voltage Vchannel of the program inhibited cell transistor is boosted by applying a high voltage, e.g. a program voltage Vpgm, to the selected word line, and applying a lower, e.g. a pass voltage Vpass, to the unselected word lines. Thus, Fowler-Nordheim (F-N) tunneling is prevented between a floating gate and the channel region. This retains the initial erased state of the program inhibited cell transistor. A time period for such an operation is referred to “a program period”. After programming for the select memory cell is complete, a recovery operation for discharging charges of the bit line is performed.
The program inhibit method employing the self-boosting scheme has a problem when applied to the flash memory device. Typically, the interval between adjacent signal lines decreases in accordance with the increasing integration of the device, so that coupling between the lines readily occurs due to parasitic capacitance between adjacent signal lines. To program a memory cell, e.g. MC
15
, adjacent the string select transistor SST, when the program voltage Vpgm is applied to a select word line WL
15
connected to the memory cell MC
15
, a nominal voltage of the string select line SSL is boosted higher than the power supply voltage Vcc due to the coupling with the select word line WL
15
. This is shown in FIG.
2
. The voltage rise of the string select line SSL causes the charges produced by the self-boosting operation in the channel of the program inhibit cell transistor to go out to the unselected bit line. In other words, as shown in
FIG. 2
, the channel voltage Vchannel of the program inhibited cell transistor (or an inhibit voltage Vinhibit) is lowered by &Dgr;V in proportion to the voltage rise of the string select line SSL. Thus, a program disturb where the program inhibited cell transistor is programmed undesirably occurs.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a non-volatile semiconductor memory device capable of preventing program disturb that might otherwise occur while programming a memory cell adjacent to a string select line, and a program method thereof.
In order to attain the above objects, according to an aspect of the present invention, there is provided a method of programming in a non-volatile semiconductor memory device. The memory device includes a memory cell array formed of a plurality of cell strings each of which is connected through a first and second select transistors between a bit line and a common source line and

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