Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-08-06
2003-06-17
Pham, Long (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S314000, C257S316000, C438S257000, C438S435000, C438S437000
Reexamination Certificate
active
06580117
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device and a method of manufacturing the same, and more particularly to a structure of a non-volatile semiconductor memory device and a method of manufacturing the same, wherein reduction in thickness of an insulating film in the vicinity of a peripheral edge of an element-isolating insulating film can be prevented, while the occurrence of crystal defect attributable to expansion of the element-isolating insulating film can be prevented.
2. Description of the Background Art
Conventionally, a Shallow Trench Isolation (STI) for increasing the density of a non-volatile semiconductor memory device is known. This STI is implemented by forming a trench in a semiconductor substrate, filling it with an insulating film such as a silicon oxide film, and planarizing that insulating film.
FIG. 30
shows a cross-sectional view of a conventional non-volatile semiconductor memory device employing the aforementioned STI.
As shown in
FIG. 30
, the non-volatile semiconductor memory device includes a peripheral circuit portion and a memory cell portion. A trench for element-isolation
29
and a silicon oxide film
21
are formed on the main surface of a semiconductor substrate
1
in the peripheral circuit portion, and a trench for element-isolation
3
and a silicon oxide film
21
are formed on the main surface of semiconductor substrate
1
of the memory cell portion. A nitrided silicon layer
25
is formed on the wall surfaces of trenches
3
and
29
.
In the memory cell portion, there is formed a memory cell transistor having a floating gate electrode
8
formed above the main surface of semiconductor substrate
1
with a thermal oxide film
4
interposed, an insulating film
9
, and a control gate electrode
35
.
Floating gate electrode
8
is formed of a doped polysilicon film
6
, and control gate electrode
35
has a doped polysilicon film
10
and a WSi film
11
. A silicon oxide film
12
is formed on control gate electrode
35
.
In the peripheral circuit portion, there is formed an MOS (Metal Oxide Semiconductor) transistor having a gate electrode
13
formed above the semiconductor substrate
1
with a thermal oxide film
5
interposed. The gate electrode
13
has doped polysilicon film
10
and WSi film
11
. The silicon oxide film
12
is also formed on gate electrode
13
.
An interlayer insulating film
14
is formed to cover the above-mentioned memory cell transistor and MOS transistor. The interlayer insulating film
14
has a contact hole
15
, in which a W plug
16
is formed. On interlayer insulating film
14
, an interconnection film
17
is formed, which is electrically connected with W plug
16
.
Referring now to
FIGS. 31
to
41
, a method of manufacturing the non-volatile semiconductor memory device having the aforementioned structure will be described.
As shown in
FIG. 31
, a thermal oxide film
30
is formed on the main surface of semiconductor substrate
1
, and a silicon nitride film
18
is formed on the thermal oxide film
30
. A photoresist
34
is formed to have a predetermined shape on silicon nitride film
18
by photolithography. Silicon nitride film
18
and thermal oxide film
30
are etched using photoresist
34
as a mask.
After removal of photoresist
34
, semiconductor substrate
1
is etched using silicon nitride film
18
as a mask to form trench
3
as shown in FIG.
32
. The inner wall of trench
3
is nitrided with NO, N
2
O or the like to form nitrided silicon layer
25
.
Then, silicon oxide film
21
is deposited to fill in trench
3
as shown in FIG.
33
. Thereafter, as shown in
FIG. 34
, CMP (Chemical Mechanical Polishing) is performed for silicon oxide film
21
.
As shown in
FIG. 35
, silicon oxide film
21
is then wet-etched by a predetermined amount with hydrofluoric acid, silicon nitride layer
18
is removed by hot phosphoric acid, and thermal oxide film
30
is removed by hydrofluoric acid.
Then, a thermal oxide film
4
is formed, which will serve as a tunnel oxide film in the memory cell portion. At this point as shown in
FIG. 36
, in a region
40
where nitrided silicon layer
25
appears on the surface of semiconductor substrate
1
, thermal oxide film
4
becomes locally thin, so that a thin portion
4
a
is formed in thermal oxide film
4
at the periphery of the element-isolating oxide film.
On the thermal oxide film
4
, a doped polysilicon film
6
is formed, and on the doped polysilicon film
6
, a photoresist
36
is formed. Doped polysilicon film
6
is etched using this photoresist
36
as a mask, as shown in FIG.
37
.
After removal of photoresist
36
, insulating film
9
is deposited on doped polysilicon film
6
, and a photoresist
37
is formed to have a predetermined shape on insulating film
9
as shown in FIG.
38
. Being etched using this photoresist
37
as a mask, insulating film
9
, doped polysilicon film
6
, and thermal oxide film
4
on the peripheral circuit portion are removed.
Then, as shown in
FIG. 39
, thermal oxide film
5
is formed on the peripheral circuit portion. At this point, in a region where nitrided silicon layer
25
appears on the surface of semiconductor substrate
1
, thermal oxide film
5
becomes locally thin, so that a thin portion is formed in thermal oxide film
5
at the periphery of the element-isolating oxide film.
Doped polysilicon film
10
, WSi film
11
and silicon oxide film
12
are deposited on thermal oxide film
5
and insulating film
9
. As shown in
FIG. 39
, a photoresist
38
is formed to have a predetermined shape on silicon oxide film
12
, and silicon oxide film
12
is etched using photoresist
38
as a mask.
After removal of photoresist
38
, WSi film
11
and doped polysilicon film
10
are etched using silicon oxide film
12
as a mask. Accordingly, as shown in
FIG. 40
, control gate electrode
35
in the memory cell portion and gate electrode
13
of MOS transistor in the peripheral circuit portion are formed.
Thereafter, as shown in
FIG. 41
, a photoresist
39
covering the peripheral circuit portion is formed, and insulating film
9
and doped polysilicon film
6
in the memory cell portion are etched using photoresist
39
as a mask. Accordingly, floating gate electrode
8
of the memory cell portion is formed.
Then, following a prescribed impurity implantation, interlayer-insulating film
14
is deposited. In this interlayer insulating film
14
, a contact hole
15
is formed, in which the W plug is formed. Interconnection film
17
is formed on interlayer insulating film
14
. Through the above steps, the non-volatile semiconductor memory device shown in
FIG. 30
is formed.
When a thermal oxidation process is performed for forming the above mentioned thermal oxide film
4
and the like, oxidation may possibly develop from the inner wall of the trench, and the filled silicon oxide film
21
may undesirably expand. When silicon oxide film
21
expands, a large stress is exerted onto semiconductor substrate
1
to adversely increase crystal defect density in semiconductor substrate
1
.
In the non-volatile semiconductor memory device shown in
FIG. 30
, however, nitrided silicon layer
25
is formed on the inner walls of trenches
3
and
29
, so that the aforementioned expansion of silicon oxide film
21
can be prevented, and thus increase in crystal defect density in semiconductor substrate
1
can be prevented.
On the other hand, since nitrided silicon layer
25
reaches up to the main surface of semiconductor substrate
1
as shown in
FIG. 35
, upon formation of thermal oxide film
4
in the subsequent step, the growth of thermal oxide film
4
is inhibited on nitrided silicon layer
25
. Therefore, as shown in
FIG. 36
, the thermal oxide film
4
is reduced in thickness on nitrided silicon layer
25
, resulting in formation of thin portion
4
a
as previously mentioned.
Presence of such thin portion
4
a
lowers a breakdown voltage in this portion, for example, to make it difficult to ensure the desired electric chara
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Pham Long
LandOfFree
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