Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2000-01-19
2003-04-22
Zarabian, Amir (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S165000, C438S278000, C438S637000
Reexamination Certificate
active
06551867
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device having a floating gate and a control gate which is formed to overlap the floating gate through a tunneling oxide film covering the floating gate, and a method of manufacturing it, and more particularly to technology for preventing a reduction in the erasure efficiency when data erasure is repeated by extracting charges (electrons) stored in the floating gate towards the control gate, thereby extending the operation life (cycle life) of a memory cell.
2. Description of the Related Art
In an electrically erasable non-volatile semiconductor memory device composed of memory cells each consisting of a single transistor, particularly a programmable ROM (EEPROM: Electrically Erasable and Programmable ROM, also referred to as “flash memory”), each memory cell consists of a transistor in a double-gate structure having a floating gate and a control gate. In such a memory cell transistor in a double gate structure, write of data is performed by accelerating hot electrons generated on the side of a drain region so as to be injected into the floating gate. Erasure of data is performed by extracting charges from the floating gate to the control gate through F-N tunneling (Fowler-Nordheim tunneling).
FIG. 10
is a plan view of a memory cell portion of a non-volatile semiconductor memory device having a floating gate.
FIG. 11
is a sectional view taken in line X
1
—X
1
in FIG.
10
. The memory cell portion adopts a split gate structure in which a control gate is arranged in parallel to a floating gate.
A plurality of element isolation films
2
of a thick LOCOS oxide film selectively formed by LOCOS (Local Oxidation of Silicon are formed in stripes on a surface area of a P-type semiconductor substrate
1
so that element areas are sectioned from one another. Floating gates
4
are formed on the semiconductor substrate
1
so that each of them extends between adjacent element isolation films
2
through an oxide film
3
A. The floating gate
4
is arranged individually in each memory cell. By selective oxidation, a selective oxide film
5
on the floating gate
4
is formed to be thicker in the central area and have an acute corner on the edge thereof so that concentration of an electric field is likely to occur at the edge of the floating gate
4
during data erasure.
On the semiconductor substrate
1
on which the plurality of floating gates
4
are arranged, control gates
6
are arranged so as to correspond to the respective columns of the floating gates
4
through the tunneling oxide film
3
integrated to the oxide films
3
A. The control gate
6
partially overlaps the floating gate
4
and the remaining portion thereof abuts on the semiconductor substrate
1
through the oxide film
3
A. The floating gates
4
and the control gates
6
are arranged so that they are symmetrical from each other in adjacent columns.
An N-type drain region
7
and a N-type source region
8
are formed in the substrate areas between the control gates
6
and between the floating gates
4
. The drain region
7
is individually surrounded by the element isolation films
2
between the control gates
6
, whereas the source region
8
extends along the control gate
6
. These floating gate
4
, control gate
6
, drain region
7
and source region
8
constitute a memory cell transistor.
A metallic wiring
10
of aluminum alloy is arranged on the control gate
6
in a direction perpendicular to the control gate through an interlayer insulating film
9
. The metallic wiring
10
is connected to the drain region
8
through a contact hole
11
. Each control gate
6
serves as a word line whereas the source region
8
extending along the control gate
6
serves as a source line. The metallic wiring
10
connected to the drain region
7
serves as a bit line.
In the case of the memory cell transistor in a double gate structure, the “on” resistance between the source and drain varies according to the quantity of charges injected into the floating gate
4
. Therefore, by selectively injecting the charges into the floating gate
4
so that the “on” resistance of a specific memory cell transistor is varied, a difference thus produced in the operation characteristic of each memory cell transistor is correlated with the data to be stored.
The respective operations of write, erasure and read of data in the non-volatile semiconductor memory device can be performed in the following manner. In the write of data(data writing operation), the potential of the control gate
6
is set at 2 V; the potential of the drain region
7
is set at 0.5 V and the high potential of the source region
8
is set at 12 V. In this case, the potential of the floating gate
4
is elevated to about 9 V because of the difference in the capacitive couplings between the control gate
6
and floating gate
4
and between the floating gate
4
and substrate (source region
8
) (i.e. capacitance between the control gate
6
and floating gate
4
<capacitance between the floating gate
4
and substrate). Thus, the hot electrons generated in the vicinity of the drain region are accelerated toward the floating gate
4
and injected into the floating gate
4
through the oxide film
3
A, thereby making the write of data.
In the erasure of data(data-erasing operation), the potential of each of the drain region
7
and source region
8
is set at 0 V and that of the control gate
6
is set at 14 V. In this case, the charges (electrons) pass through the tunnelling oxide film
3
from the acute portion at the corner of the floating gate
4
by the F-N (Fowler-Nordheim tunneling) conduction so that they are discharged into the control gate
6
, thereby making the erasure of data.
In the read of data(data-reading operation), the potential of the control gate
6
is set at 4 V; that of the drain region
7
is set at 2 V and that of the source region
8
is set at 0 V. In this case, if the charges (electrons) have been injected in the floating gate
4
, the potential at the floating gate
4
becomes low. Therefore, no channel is formed beneath the floating gate
4
so that a drain current does not flow. In contrast, if the charges (electrons) have not been injected in the floating gate
4
, the potential of the floating gate
4
becomes high. Therefore, the channel is formed beneath the floating gate
4
so that the drain current flows.
FIG. 9
is a graph showing a measurement result (indicated by one-dot chain line) of a cycle life (number of times of the erasure/write of data: E/W Cycle) in a conventional device having the above configuration. As seen from the graph, the accumulated failure rate (%) increases with an increase of the E/W cycle. Incidentally, the “failure” in this case refers to the operation life of a memory cell when the cell current lowers to a decidable level (e.g. when the memory cell current of the memory cell in the erasure state becomes 30 &mgr;m which is 30% of the initial value of 100 &mgr;m).
As seen from the graph, in the conventional non-volatile semiconductor memory device, when the number of times of E/W of data reaches about 70,000 times, the accumulated failure rate reaches 100%.
A general programmable memory requires the E/W cycle of about 100,000 times, and that of 70,000 times is insufficient. Therefore, it has been demanded to increase the number of times of the E/W cycle.
As a result of analysis by the inventors of the present invention, it has been found that the material of the interlayer dielectric film formed on the memory cell transistor is correlated with the cycle life.
Specifically, in an device configuration in which a relatively large level difference occurs because the control gate overlaps the floating gate like the non-volatile semiconductor memory device according to the present invention, an interlayer dielectric film
9
subjected to an etch back step of a SOG (Spin On Glass) film is formed.
The inventors have supposed that the cycle life is influenced by the fact that H or OH c
Azegami Hideo
Kitazume Kazutoshi
Oya Yukihiro
Ozeki Kazuyuki
Perkins Pamela
Zarabian Amir
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