Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-11-25
2003-05-13
Crane, Sara (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S316000
Reexamination Certificate
active
06563165
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to planarization after forming an inter-layer insulating film and an arrangement of a diffusion area in drain and a diffusion area in source formed by a layer in which impurities are diffused in a non-volatile semiconductor memory device and a method for producing the same.
2. Discussion of Background
An AND-type flash memory is one type of a large-capacity non-volatile flash memory in a semiconductor memory devices. The AND-type flash memory is described, for example, in IEDM *92 Technical Digest P. 991-993, *A 1.28 &mgr;m2 contactless memory cell technology for a 3 V-only 64 M bit EEPROM*, H. Kume et al.).
FIG. 13
is an equivalent circuit diagram of a region of memory cell array of a conventional AND-type flash memory and a connecting region for connecting the region of memory cell array to a region of peripheral circuit (not shown) described in the above document. In
FIG. 13
, numerical reference
1
designates a memory cell comprises a single transistor. Numerical reference
2
designates a floating gate of the transistor comprising the memory cell
1
, which floating gate is composed of a plurality of conductive layers as described below. Numerical reference
3
designates a control gate; numerical references
4
and
5
respectively designate a local data line and a local source line, both of which are mode of an N+ diffusion layer; numerical reference
6
designates a grovel data line made of a metallic wire; numerical reference
7
designates a common source line which is connected to ground potential; numerical reference
8
designates a first selection transistor for connecting the grovel data line
6
to the local data line
4
; numerical reference
9
designates a second selection transistor for connecting the local source line
5
to the common source line
7
; numerical reference
10
designates a word line which is arranged at a substantially right angle with respect to the local data line and connected to the control gate
3
; numerical reference
11
designates a region of memory cell array in which the memory cells
1
are arranged in a matrix-like form; numerical reference
12
designates a region of first selection gate in which the first selection transistors
8
are arranged; and numerical reference
13
designates a region of second selection gate in which the second selection transistors
9
are arranged, wherein the region of first selection gate
12
and the region of second selection gate
13
are connecting regions adjacent to the region of memory cell array
11
and the region of peripheral circuit (not shown).
In the next, operation of the conventional AND-type flash memory described above will be briefly explained. The operation to be described below is recently improved and is different from the operation described in the above document. There are three types of operation of (a) write, (b) read, and (c) erase. A characteristic of the operation in the above AND-type flash memory is that all memory cells connected to a word line simultaneously become any one of operational conditions among the above three types.
In
FIGS. 14
a
through
14
c
, a memory cell array in a matrix-like form of 2×2 is shown for explaining the operation. A case that a memory cells c
1
and c
2
are selected will be described, where a condition that electrons are injected into a floating gate is expressed by data of “1”, and a condition that electrons are not injected is expressed by data of “0”.
(a) Write Operation
In write operation, “1” is written in the memory cell c
1
and “0” is written in the memory cell c
2
. As shown in
FIG. 14
a
, electric potential of a word line w
1
to be selected is 18 V; electric potential of a non-selecting word line w
2
is 4.5 V; electric potential of a local data line d
1
connected to the memory cell c
1
is 0 V; electric potential of a local data line connected to the memory cell c
2
is 6.5 V; local source lines s
1
, s
2
are in an opened state, (i.e. floating); and electric potential of a substrate is 0 V. Under such a condition, because a potential difference between the word line w
1
and the local data line d
1
is large, “1” is written in only the floating gate of memory cell c
1
by injecting electrons thereinto.
(b) Read Operation
In read operation, data written in the write operation, namely “1” from the memory cell c
1
and “0” from the memory cell c
2
, are read out. As shown in
FIG. 14
b
, electric potential of the word line to be selected w
1
is 5 V; electric potential of the non-selecting word line w
2
is 0 V; electric potential of local data lines d
1
, d
2
is 1 V; electric potential of local source lines s
1
, s
2
is 0 V; and electric potential of the substrate is 0 V. Under such a condition, because electrons are injected into a floating gate of memory cell c
1
, Vth is high and therefore an electric current does not flow into the local data line d
1
, a transistor of the memory cell c
1
, and the local source line s
1
. On the contrary, because electrons are not implanted into a floating gate of memory cell c
2
, Vth is low and therefore an electric current flows into the local data line d
2
, a transistor of the memory cell c
2
, and the local source line s
2
.
(c) Erase Operation
In erase operation, a word “erase” means that all of the data written in the write operation are changed to “0”. As shown in
FIG. 14
c
, electric potential of the word line w
1
to be selected is −18 V; electric potential of the non-selecting word line w
2
is 0 V; electric potential of the local data lines d
1
, d
2
is 0 V; the local source lines s
1
, s
2
are in an opened state; and electric potential of the substrate is 0 V. Accordingly, electrons are drawn out from the floating gate of memory cell c
1
and thereby the memory cells c
1
and c
2
have data of “0”.
In the next, layout pattern after forming a first metallic film (i.e. first metal) is shown in
FIG. 15
, which corresponds to the region of memory cell array
11
and the region of first selection gate
12
in FIG.
13
. Hereinbelow, portions of the layout pattern of
FIG. 15
are explained in correspondence with circuit components of the equivalent circuit diagram of FIG.
13
. The floating gate
2
shown in
FIG. 13
is composed of two layers of polysilicon. Although amorphous silicon can substitutes for polysilicon, a case that polysilicon is used will be described hereinbelow. Numerical reference
21
of
FIG. 15
designates a lower floating gate made of first polysilicon; and numerical reference
22
designates an upper floating gate made of second polysilicon. Numerical reference
23
of
FIG. 15
designates third polysilicon for composing the control gate
3
and the word line
10
of
FIG. 13
, wherein although the third polysilicon may be substituted by a double-layer structure of polysilicon and silicide for reducing resistance, a case that polysilicon is used will be described hereinbelow. Numerical reference
24
of
FIG. 15
designates a diffused area in drain of the transistors of the memory cell, which area is made of an N+ diffusion layer. Hereinbelow, this diffused area in drain is referred to as a drain area. The drain area corresponds to the local data line
4
of FIG.
13
. Numerical reference
25
of
FIG. 15
is a diffused area in source of the transistors of the memory cell, which area is made of an N+ diffusion layer. Hereinbelow, the diffused area in source is referred to as a source area. The source area corresponds to the local source line
5
of FIG.
13
. Numerical reference
26
of
FIG. 15
corresponds to the grovel data line
6
of
FIG. 13
made of a first metal; numerical reference
27
designates a drain source area of the first selection transistor
8
; numerical reference
28
designates a gate of the first selection transistor
8
made of the third polysilicon; numerical reference
29
designates a metal contact for connecting the grovel data line
26
to the drain source area
27
of the first selection transistor; an
Kuriyama Hirotada
Sakakibara Kiyohiko
Crane Sara
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
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