Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2000-11-28
2004-08-24
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S201000
Reexamination Certificate
active
06781895
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device using a flash EEPROM, and a memory system using such a memory device.
2. Description of the Related Art
Magnetic disks have been used widely as storage means for computer systems. A magnetic disk has the following disadvantages. Namely, it is weak against an impact force because of its highly precise drive mechanism, less portable because of its weight, difficult to drive with a battery because of large power consumption, unable to access at high speed, and so on.
In order to overcome such disadvantages, semiconductor memory devices using an EEPROM have been developed recently. Generally, a semiconductor memory device has the following advantages over a magnetic disk. Namely, it is strong against an impact force because it has no highly precise drive mechanism, more portable because of its light weight, easy to drive with a battery because of small power consumption, able to access at high speed, and so on.
As an example of EEPROM, there is known a NAND cell type EEPROM capable of providing a high integration density. Such an EEPROM has the following structure. Namely, a plurality of memory cells are disposed, for example, in a column direction. The source and drain of adjacent memory cells are sequentially connected in series. With such a connection, a unit cell group (NAND cell) is constituted by a plurality of memory cells connected in series. Such a unit cell group is connected to each bit line.
A memory cell generally has a MOSFET structure with laminated charge accumulation layer and control gate. Memory cells are integrated as an array within a p-type well formed in a p-type or n-type substrate. The drain side of a NAND cell is connected via a select gate to a bit line. The source side of a NAND cell is connected via a select gate to a source line (reference potential wiring). The control gate of each memory cell is connected to a word line arranged in a row direction.
The write operation of a NAND type EEPROM is performed in the following manner. The threshold value or threshold voltage of all memory cells within a NAND cell is set to a negative value by the preceding erase operation. Data is sequentially written starting from the memory cell remotest from the bit line. A high voltage Vpp (about 20 V) is applied to the control gate of the selected memory cell. An intermediate potential VM (about 10 V) is applied to the control gates and select gates of the other memory cells on the bit line side. A potential of 0 V or intermediate potential is applied to the bit line, depending upon the level of write data. When a potential of 0 V is applied to the bit line, this potential is transmitted to the drain of the selected memory cell, so that electrons are injected from the drain to the floating gate. As a result, the threshold value of the selected memory cell is shifted to the positive side. This state is called, for example, a “0” state. If an intermediate potential is applied to the bit line, electron injection does not occur. As a result, the threshold value of the selected memory will not change. Namely, the threshold value takes a negative value. This state is called a “1” state.
In the erase operation, data in all memory cells within the NAND cell are erased at the same time. Namely, 0 V is applied to all control gates and select gates to make the bit lines and source lines in a floating state, and a high voltage 20 V is applied to the p-type well and n-type substrate. As a result, electrons in floating gates of all memory cells are removed therefrom to the p-type well, shifting the threshold values of memory cells toward the negative side.
The data read operation is performed in the following manner. Namely, 0 V is applied to the control gate of the selected memory cell, and a power supply voltage Vcc (=5 V) is applied to the control gates and select gates of non-selected memory cells. In this state, it is checked whether current flows through the selected memory cell. If current flows, it means that data “1” was stored, whereas if no current flows, it means that data “0” was stored.
As apparent from the description of the above operations, in a NAND cell type EEPROM, non-selected memory cells operate as transfer gates during the data read/write operation. For this reason, there is a limit of a threshold voltage of a memory cell written with data. For example, the proper range of the threshold value of a memory cell written with “0” should be from 0.5 V to 3.5 V. This range is required to be narrower when considering a change of the threshold value with time after data write, variation of characteristic parameters of memory cells, and variation of power supply voltages.
However, it is difficult for a conventional data write method to make the range of the threshold value of a memory cell written with data 110″ enter such an allowable range, because the conventional data write method writes data by using the same condition for all memory cells while using a fixed write potential and write time for all memory cells. More specifically, the characteristic of each memory cell changes with variation of manufacturing processes, sometimes resulting in a memory cell easy to be written and at other times resulting in a memory cell difficult to be written. Considering such a write characteristic difference, there has been proposed a data write method which controls the data write time for verifying the written data, in order to set the threshold value of each memory cell within a desired range.
With this method, however, data in a memory cell is required to be outputted from the memory device in order to check whether data has been written properly, posing a problem of a longer total write time.
For an erase verify operation, there is known a technique as disclosed in Japanese Patent Laid-Open Publication No. 3-259499, whereby outputs of a plurality of sense amplifiers are supplied to an AND gate, and the logical operation result is used in generating a collective erase verify signal. However, this circuit configuration can be used only for the NOR type erase verify operation, and it cannot be applied to the write verify operation. The reason for this is that the values of write data take “1” and “0” and the logical operation of the sense amplifier outputs cannot be used for a collective verify operation. For this reason, it becomes necessary for a data write operation to repetitively execute the write operation and verify read operation and sequentially output data of each memory cell, hindering the high speed data write operation.
SUMMARY OF THE INVENTION
The present invention pays attention to the above-described difficulty of high speed operation, and aims at providing an EEPROM and a memory system using an EEPROM capable of providing a high speed write operation and write verify operation and a high speed erase operation and erase verify operation, without increasing the area of necessary control circuits.
According to the memory device of the present invention, each of the plurality of comparator means compares the data stored in the data latch means with the data read from the memory cell, and judges whether data was written in the memory cell. The collective verify means outputs the write completion signal when all of the plurality of comparator means judge that data was written in corresponding memory cells.
According to the memory device of the present invention, externally inputted write data is stored in each of the plurality of data latch means as first and second logical levels. Each of the plurality of memory cells stores data as an erase state when the threshold value of each memory cell is within the first range and as a write state when the threshold value of each memory cell is within the second range. In a write operation, the threshold value is changed/change-suppressed when the first/second logical level is stored in each data latch means. In a verify operation after the write operation, the data stored in the dat
Aritome Seiichi
Asano Masamichi
Itoh Yasuo
Iwata Yoshihisa
Kato Hideo
Foley & Lardner LLP
Le Vu A.
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