Non-volatile semiconductor memory device and memory circuit usin

Static information storage and retrieval – Floating gate – Particular biasing

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Details

365 94, 365102, 257316, 257319, 257321, G11C 1134

Patent

active

054023742

ABSTRACT:
In the non-volatile semiconductor memory device according to the present invention, a floating gate is provided on a channel region which is interposed between a source region and a drain region through a tunnel insulation film. The tunnel insulation film and the floating gate are formed spaced apart from the source region by a predetermined offset distance. A sidewall gate which is insulated from the channel region and the floating gate is provided in an offset distance portion on the channel region. An offset region immediately under the sidewall gate functions as an inversion layer, thereby to make it possible to read out information at high speed utilizing the inversion of the offset region.

REFERENCES:
patent: 5274586 (1993-12-01), Matsukawa
patent: 5313427 (1994-05-01), Schreck et al.
patent: 5338954 (1994-08-01), Shimoji
patent: 5345104 (1994-09-01), Prall et al.

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