Method of fabricating DRAM cell with self-aligned contact

Details Method of fabricating DRAM cell with self-aligned contact Method of fabricating DRAM cell with self-aligned contact

1996-05-29

1997-09-30

Tsai, Jey

Fishing, trapping, and vermin destroying

437 60, 437919, H01L 218242

Patent

active

056725353

ABSTRACT:
A structure and method are provided for reducing DRAM cell area by eliminating the contact-to-gate spacing requirement while increasing the capacitor area by designing the capacitor to extend inside the contact, without sacrificing the sidewall capacitance. The new structure uses a self-aligned contact where the contact can overlap the gate region in the layout.

REFERENCES:
patent: 5053351 (1991-10-01), Fazan et al.
patent: 5126916 (1992-06-01), Tseng
patent: 5262662 (1993-11-01), Gonzalez et al.
patent: 5429976 (1995-07-01), Hong et al.
patent: 5434812 (1995-07-01), Tseng
patent: 5504704 (1996-04-01), Sato et al.

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