Non-volatile semiconductor memory device and manufacturing metho

Details Non-volatile semiconductor memory device and manufacturing metho Non-volatile semiconductor memory device and manufacturing metho

1992-11-13

1994-07-05

Prenty, Mark V.

Undertaking

257316, 257321, 257773, 257774, 365185, H01L 2968, G11C 1134

Patent

active

053269993

ABSTRACT:
Disclosed is a non-volatile semiconductor memory device and the manufacturing method thereof. The non-volatile semiconductor memory device comprising a semiconductor substrate, and a group of gates electrically isolated from each other and formed on the semiconductor substrate, wherein the group of gates comprises a floating gate formed with a first conductive layer, a control gate formed with a second conductive layer laminated on the floating gate and select gates formed with the first conductive layer and the second conductive layer/formed on both the opposite side of the floating gate and the control gate and with an interposing impurity diffusion region formed on the semiconductor substrate, and wherein the select gates formed with the first conductive layer and the second conductive layer forms contacts on a field oxidation layer, thereby being connected with each other. The gate of the select transistor is formed as a first conductive layer by a self-aligned etching process and a butted contact process. Meanwhile, prior to forming a tunnel oxidized film, a buried n.sup.- layer is formed on a tunnel region pattern so as to be self-aligned, thereby reducing a distance between the select transistor and the storage transistor to within photolithographic processing limits so as to realize the high-integration of the EEPROM.

REFERENCES:
patent: 5200636 (1993-04-01), Uemura et al.

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