Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-01-26
2003-10-21
Tran, Thien F (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S316000, C257S317000, C257S321000
Reexamination Certificate
active
06635920
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device and manufacturing method thereof and, more particularly, to a structure of a memory cell transistor in a non-volatile semiconductor memory device and manufacturing method thereof.
2. Description of the Background Art
Conventionally, a DiNOR (Divided bit line NOR) type flash memory is known as a non-volatile semiconductor memory device.
FIGS. 12 and 13
show an example of a manufacturing method for a memory cell transistor in a conventional DINOR type flash memory.
As shown in
FIG. 12
, a multilayered structure of a gate isolation film
5
, a first polysilicon film
2
a,
an isolation film
6
, a second polysilicon film
2
b,
a silicide film
2
c
and an isolation film
7
is formed on the main surface of a semiconductor substrate
1
.
Next, a resist
8
is formed so as to cover regions where source regions of memory cell transistors are formed and to expose regions where drain regions are formed. Using this resist
8
as a mask, P and As are, respectively, implanted into the main surface of the semiconductor substrate
1
. Thereby, drain regions
12
which have n
−
impurity regions
12
a
and n
+
impurity regions
12
b
are formed.
Next, as shown in
FIG. 13
, a resist
8
is formed so as to cover the drain regions
12
of the memory cell transistors and to expose the regions where the source regions are formed. Using this resist
8
as a mask, As and B are, respectively, implanted into the main surface of the semiconductor substrate
1
. Thereby, source regions
11
which have p
−
impurity regions
11
a
and n
+
impurity regions
11
b
are formed.
A conventional DINOR type flash memory which has the above described structure carries out writing by utilizing the FN tunnel phenomenon so as to draw out electrons from the FG to the drain region
12
and carries out erasing by utilizing the FN tunnel phenomenon so as to inject electrons from the entire surface of the channel region into the FG. Therefore, though high speed erasing is possible, writing is slow (approximately 1 ms), which raises the problem of making a byte program difficult.
SUMMARY OF THE INVENTION
Then, the present invention is provided in order to solve the above described problem. The purpose of the present invention is to provide a non-volatile semiconductor memory device which can carry out both the writing operation and the erasing operation at high speed.
According to one aspect of the present invention, a non-volatile semiconductor memory device is provided with a semiconductor substrate having a main surface, source and drain regions of memory cell transistors formed on the surface, and gates of the memory cell transistors which are formed on the main surface via a gate isolation film and which are located between the source and the drain regions. Then, the source regions include first high impurity concentration regions of a first conductive type and first low impurity concentration regions of a second conductive type while the drain regions include second high impurity concentration regions of a first conductive type and second low impurity concentration regions of a second conductive type.
The present inventors have endeavored to gain a non-volatile semiconductor memory device which can carry out both the writing and the erasing operations at high speed and have devised a combination of channel hot electron (hereinafter referred to as “CHE” ) writing and erasing on the entire surface of the channel. That is to say, writing is carried out by injecting CHEs into the FG and erasing is carried out by utilizing the FN tunnel phenomenon on the entire surface of the channel so as to draw out electrons from the FG. In this way, by adopting the CHE writing, high speed byte writing can be carried out while, by carrying out the erasing which utilizes the FN tunnel phenomenon on the entire surface of the channel (hereinafter referred to “erasing on the entire surface of the channel” ), the erasing operation can be carried out at high speed. Therefore, the present inventors have further endeavored to gain a memory cell transistor structure which can be adopted in a related non-volatile semiconductor memory device and also have devised the above described structure. This structure is provided with the drain regions having the second high impurity concentration regions of the first conductive type and the second low impurity concentration regions of the second conductive type and, thereby, it is possible to make CHEs occur in the vicinity of the drain regions so as to enable the effective carrying out of the CHE writing. In addition, at the time of erasing, the erasing on the entire surface of the channel can be carried out by applying a predetermined voltage to the gates, to the source regions of the memory cell transistors and to the substrate.
It is preferable that the impurity concentration of the first conductive type included in the first high impurity concentration regions be higher than the impurity concentration of the first conductive type included in the second high impurity concentration regions and the impurity concentration of the second conductive type included in the first low impurity concentration regions is the same as, or is higher than, the impurity concentration of the second conductive type included in the second low impurity concentration regions.
Thereby, as shown in
FIG. 9
, for example, the junction withstand voltage (BVds) between the source region and the drain region can be maintained even in the case that the gate length is made shorter. At this time the resistance of the source region can also be maintained at a low level. In addition, by properly adjusting the impurity concentration of the second conductive type, the threshold voltage (UV-Vth) under the initial condition of the memory cell transistor can be set at a desired value.
It is preferable that the first high impurity concentration regions be formed within the first low impurity concentration regions while the second high impurity concentration regions be formed within the second low impurity concentration regions.
In this way, by surrounding the high impurity concentration regions with the low impurity concentration regions, the junction withstand voltage between the source regions and the drain regions can be maintained.
It is preferable that the impurity concentration of the first conductive type included in the first high impurity concentration regions be two or more times as high as the impurity concentration of the first conductive type included in the second high impurity concentration regions while the impurity concentration of the second conductive type included in the first low impurity concentration regions is two or more times as high as the impurity concentration of the second conductive type included in the second low impurity concentration regions. Thereby, the above described effects become more evident.
The impurity concentration of the first conductive type included in the first high impurity concentration regions is two or more times as high as the impurity concentration of the first conductive type included in the second high impurity concentration regions while the impurity concentration of the second conductive type included in the first low impurity concentration regions is equal to the impurity concentration of the second conductive type included in the second low impurity concentration regions. In this case also, the above described effects become more evident.
The impurity of the first conductive type is an n type impurity while the impurity of the second conductive type is a p type impurity. The gate length of the memory cell transistors is 0.2 &mgr;m or less. In this case, the present invention becomes especially useful.
According to another aspect of the present invention, a non-volatile semiconductor memory device is provided with a semiconductor substrate having a main surface, source regions and drain regions of memory cell transistors fo
Fukumoto Atsushi
Ohnakado Takahiro
Shimizu Satoshi
McDermott & Will & Emery
Tran Thien F
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