Non-volatile semiconductor memory device and fabrication...

Details Non-volatile semiconductor memory device and fabrication... Non-volatile semiconductor memory device and fabrication...

2001-09-27

2002-12-10

Booth, Richard (Department: 2812)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C438S258000, C257S321000

Reexamination Certificate

active

06492677

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
The present application is based on Japanese priority application No. 2000-351444 filed on Nov. 17, 2000, the entire contents of which are hereby incorporated by reference.
BACKGROUND OF THE INVENTION
This invention relates to semiconductor devices generally. Especially it is related to a non-volatile semiconductor memory and fabrication process thereof.
A flash memory is a non-volatile semiconductor memory that has a simple device structure suitable for high-density integration similar to DRAMs. Thus, it is used in the various information processing apparatuses including computers and cellular phones widely. Generally, a flash memory stores information in a floating gate electrode in the form of electric charges.
Recently, a non-volatile semiconductor memory having a MONOS (metal-oxide-nitride-oxide-semiconductor) structure or SONOS (semiconductor-oxide-nitride-oxide-semiconductor) structure has been proposed. These non-volatile semiconductor memory devices use an insulation film having an ONO structure for the gate insulation film of the MOS transistor and stores information in the ONO gate insulation film in the form of electric charges.
In the non-volatile semiconductor memory of such a MONOS structure or SONOS structure, injection of electric charges into gate insulation film is conducted from a drain side or a source side. As a result, storage of multivalent information becomes possible.
FIG. 1
is a diagram that shows the circuit construction of a NOR/AND type non-volatile semiconductor memory
10
that has a conventional SONOS structure.
FIG. 1
is referred to.
The non-volatile semiconductor memory
10
has a memory cell array M that includes plural memory cell transistors M
11
-M
mm
, each having a gate insulation film of the ONO structure. In the memory cell array M, the memory cell transistors are arranged in a matrix formation. A group of memory cell transistors aligned in a row direction in the memory cell array M are connected commonly to any of the word lines WL
n
, WL
n+1
, WL
n+2
, WL
n+3
. . . extending in a row direction at the respective gate electrodes. Furthermore, a group of memory cell transistors that are aligned in a column direction are connected in memory cell array M commonly to any of the data bit lines DBL
h+1
, DBL
h+2
, DBL
h+3
, DBL
h+4
that extend in the column direction at the source diffusion region and the drain diffusion region.
Furthermore the non-volatile semiconductor memory
10
has select gate lines SG
1,2,3,4
, . . . The data bit lines DBL
h
and DBL
h+2
are connected to the corresponding main bit lines MBL
h
by select transistors T
1
and T
2
connected to the select gate lines SG
1
and SG
2
. Also, the data bit lines DBL
h+1
and DBL
h+3
are connected to the corresponding main bit line MBL
h+l
by select transistors T
3
and T
4
connected to select gate lines SG
3
and SG
4
.
In, such a construction, information is written into the gate insulation film of the memory cell transistors M
11
, M
12
, . . . that has the ONO structure in the form of channel hot-electrons injected from the source region or drain region. The electric charges thus injected are held stably in the ONO film.
FIG. 2
shows the construction of a transistor
20
that constitutes the memory cell transistor M
11
, M
12
, . . . in the memory cell array M.
FIG. 2
is referred to.
The transistor
20
is formed of on a Si substrate
21
. In the Si substrate
21
, there are formed buried diffusion regions
21
A and
21
B respectively as the source region and drain region. Furthermore the surface of substrate
21
is covered with an ONO film
22
of the structure in which an oxide film
22
a,
a nitride film
22
b
and an oxide film
22
c
are stacked. Further, a polysilicon gate electrode
23
is formed on the ONO film
22
.
FIGS. 3A and 3B
are diagrams that show the writing operation and the erasing operation carried out in the memory cell transistor of
FIG. 2
, respectively.
FIG. 3A
is referred to.
A source region
21
A is grounded at the time of the writing of information and a large positive voltage +V
w
is applied to the drain region
21
B. Further, a large positive voltage +VG
1
is applied to the gate electrode
23
. As a result, hot-electrons are formed in the channel as a result of acceleration of electrons at the drain edge of the channel region. The hot-electrons thus formed are then injected into the ONO film
22
. The hot electrons thus injected are held in the ONO film
22
in the vicinity of the drain edge. By exchanging the drive voltage that is applied to the drain region
21
B and the source region
21
A, it is also possible to carry out the injection of the hot electrons similarly in the vicinity of the source edge of the ONO film
22
. As represented in
FIG. 1
, it becomes possible to write 2 bits of information for every one cell in the memory cell transistor
20
of FIG.
2
.
When deleting information that is already written, a large positive voltage +Ve is applied to drain region
21
B as represented in FIG.
3
B. Furthermore a large negative voltage −VG
2
is applied to the gate electrode
23
. With this, holes are injected from drain region
21
B into the ONO film
22
. As a result, the electric charges that are accumulated in the vicinity of the drain edge in ONO film
22
are annihilated. In the case the electrons are accumulated in the vicinity of the source edge in ONO film
22
, it is sufficient to carry out the hole-injection from source region
21
A.
When reading out information written in the vicinity of the drain edge of the ONO film
22
, a specified gate voltage Vg is applied to gate electrode
23
as represented in FIG.
4
A. Further, the drain region
21
B is grounded and the source region
21
A is applied with a reading voltage Vr. As a result, it becomes possible for the careers to flow to the source region
21
A from the drain region
21
B through the channel formed in the Si substrate
21
right underneath the gate electrode
23
, provided that electron are not accumulated in the vicinity of the drain edge of the ONO film
22
. As a result, the memory cell transistor
20
conducts.
In the case the electrons are accumulated in the vicinity of the drain edge of ONO film
22
on the other hand, the channel right underneath the gate electrode
23
is blocked at the drain edge. Thus, the transistor
20
does not conduct. In the case of reading out the information written in the vicinity of the source edge of the ONO film
22
, on the other hand, the source region
21
A is grounded as represented in
FIGS. 4A and 4B
. Further, a read voltage Vr is applied to the drain region
21
B.
FIGS. 5A-5D
,
FIGS. 6A-6C
,
FIGS. 7A-7D
,
FIGS. 8A-8C
,
FIGS. 9A-9D
and FIGS.
10
A-
10
C show the fabrication process of a non-volatile semiconductor memory
10
that uses the memory cell transistor
20
.
FIGS. 5A-5D
are referred to.
FIG. 5A
is a plan view of the non-volatile semiconductor memory
10
while
FIG. 5B
shows the non-volatile semiconductor memory
10
in a cross-sectional view taken along a line X
1
-X
1
′ of FIG.
5
A.
FIG. 5C
shows the non-volatile semiconductor memory
10
in a cross-sectional view taken along a line X
2
-X
2
′ of FIG.
5
A. Further,
FIG. 5D
shows the non-volatile semiconductor memory
10
in a cross-sectional view of taken along a line X
3
-X
3
′ of FIG.
5
A.
FIGS. 5A-5D
are referred to.
An active region is defined on the Si substrate
21
by a field oxide film
21
F having a thickness of 200-500 nm formed by a thermal oxidation processes at 900-1000° C. Further, an ONO film
22
is formed on the active region. More specifically, the surface of the Si substrate
21
exposed at the active region is thermally oxidized at 800-1100° C. As a result, an oxide film
22
a
is formed with a thickness of 5-10 nm. Furthermore, a CVD process is conducted at 600-800° C. on the oxide film
22
a
. Thereby, a nitride film
22
b
is deposited with a thickness of 12-16 nm. Furthermo

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