Non-volatile semiconductor memory device allowing fast verifying

Details Non-volatile semiconductor memory device allowing fast verifying Non-volatile semiconductor memory device allowing fast verifying

1995-02-09

1996-05-28

Zarabian, A.

Static information storage and retrieval

Floating gate

Particular biasing

36518529, 365203, G11C 1134

Patent

active

055218644

ABSTRACT:
A bit line reset transistor resets every second bit line of a plurality of bit lines to be write-verified. At this time, a transfer gate disconnects a column latch from the unreset bit line. Then, the unreset bit line is precharged in accordance with data of the column latch, while applying a verify voltage to a word line. Then, a source line transistor grounds a source line, and the bit line is connected to the column latch, so that data corresponding to a value of a threshold voltage of the memory cell is held by the column latch, and a write verifying operation is performed.

REFERENCES:
patent: 5297096 (1994-03-01), Terada
patent: 5379256 (1995-01-01), Tanaka
"A Quick Intelligent Program Architecture for 3V-Only NAND-EEPROMS", Tanaka et al., 1992 Symposium on VLSI Circuits Digest of Technical Papers, pp. 20-21.

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