Non-volatile semiconductor memory device allowing concurrent...

Static information storage and retrieval – Systems using particular element – Magnetoresistive

Reexamination Certificate

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C365S189040

Reexamination Certificate

active

11179892

ABSTRACT:
A write bit line and a read bit line are provided separately for a memory cell. A source line connecting to the memory cell is formed of a source impurity region the same in conductivity type as a substrate region. A memory cell transistor and the source impurity region are connected by a metal interconnection line of a low resistance. A rise in the source line potential can be prevented, and a memory cell current can reliably be generated according to storage data. Further, fast data reading can be achieved. Additionally, by performing precharging and data amplification in a unit of read bit line, the load of the read bit line can be alleviated to achieve fast reading. An accessing time of a non-volatile semiconductor memory device that uses a variable resistance element as a storage element is reduced without increasing the current consumption.

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patent: 2003-249629 (2003-09-01), None
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Durlam et al., “A 0.18 μm 4Mb Toggling MRAM”, 2003 IEEE International Electron Devices Meeting, Published in IEDM Technical Digest 2003, Session 34, paper #0, Dec. 2003, pp. 1-3.

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