Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-03-16
2003-09-02
Eckert, George (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S321000, C257S401000, C257S900000, C365S185100
Reexamination Certificate
active
06614071
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device, more particularly to a non-volatile semiconductor memory device that can speed up both writing and erasing performances without increasing its memory cell area and be manufactured at a low cost.
2. Description of the Related Art
Improvement of both writing and erasing performances has been major demands for non-volatile semiconductor memories. In order to satisfy such demands, several types of such semiconductor memories are proposed, for example, by Japanese Laid-Open Patent Application No. 7-153857, No. 5-90610, and No. 9-312351.
FIGS. 3A through 3J
illustrate a conventional non-volatile semiconductor memory device disclosed in Japanese Laid-Open Patent Application No. 7-153857.
As illustrated in
FIG. 3A
, a field insulating film
102
is formed selectively on the surface of a p-type silicon substrate
101
so as to partition an element area. Then, an insulating film (not illustrated), a polysilicon film (not illustrated), an oxide film (not illustrated), and a nitride film (not illustrated) are formed on the element area. After this, those films are patterned to form a gate insulating film
110
, a gate polysilicon film
111
, and a laminated film
112
consisting of the oxide and nitride films sequentially and selectively. An oxide film
113
and a nitride film
114
are formed sequentially on the entire surface as illustrated in FIG.
3
B. Then, as illustrated in
FIG. 3C
, the nitride film
114
is etched back to form an insulating film
115
consisting of a nitride film on the side walls of the gate polysilicon film
111
and the laminated film
112
. After this, n-type impurities are ion-implanted on the surface of the element area using both side wall insulating film
115
and field insulating film
102
as masks, then the n-type impurities are thermodiffused thereby to form an n-type source-drain area
103
.
As illustrated in
FIG. 3D
, the surface of the element area is oxidized by heat using both side wall insulating film
115
and field insulating film
102
as masks, thereby an oxide film
104
is formed on the surface of the source-drain area
103
. After this, the nitride film in the laminated film
112
and the side wall insulating film
115
remaining on the top and side wall surfaces of the gate polysilicon film
111
as illustrated in
FIG. 3E
are removed by wet etching. The oxide film
113
is also removed by wet etching at this time. And, as illustrated in
FIG. 3F
, an oxide film
107
is formed on the top and side surfaces of the gate polysilicon film
111
, as well as on the surface of the exposed element area. The oxide film
107
is formed thinner than the gate insulating film
110
.
After this, as illustrated in
FIG. 3G
, a polysilicon layer
116
is formed on the entire surface. Then, as illustrated in
FIG. 3H
, the polysilicon layer
116
is etched back thereby to form a side wall film
117
consisting of polysilicon on the side wall of the gate polysilicon film
111
and over the top surface of the source-drain area
103
that is not covered by any of the gate polysilicon film
111
and the oxide film
104
. The oxide film
107
on the surface of the gate polysilicon film
111
is removed by wet etching. Then, as illustrated in
FIG. 3I
, a polysilicon film is formed on the entire surface and the film is patterned thereby to form a floating gate
105
consisting of this polysilicon layer, the gate polysilicon film
111
, and the side wall film
117
. After this, an interlaminar insulating film
109
is formed on the entire surface, and a control gate
106
consisting of polysilicon is formed on the entire surface, as illustrated in FIG.
3
J.
In each memory cell of such a conventional non-volatile semiconductor memory formed as described above, the oxide film
107
being in contact with the source-drain area
103
is formed thinner than the gate insulating film
110
formed under the gate polysilicon film
111
and the floating gate
105
is extended onto the oxide film
104
formed over the source-drain area
103
. Consequently, it is possible to increase the capacity ratio between the control gate
106
—floating gate
105
capacity and the floating gate
105
—substrate
101
capacity. And therefore, both writing and erasing performances of the non-volatile semiconductor memory are speeded up.
In the conventional non-volatile semiconductor memory, however, the floating gate
105
is extended onto the oxide film
104
thereby to increase the capacity ratio as described above. The source-drain area
103
must thus be designed to be longer in width than the channel, for example, to form a cotact hole. Consequently, the memory cell size exceeds the minimum design value.
In addition, according to the conventional non-volatile semiconductor memory manufacturing method, the lithographic process is needed twice, that is, the first process needed in the process for forming the gate insulating film
110
, the gate polysilicon film
111
, and the laminated film
112
illustrated in
FIG. 3B
selectively and the second process needed in the process for forming the floating gate
105
illustrated in
FIG. 3I
before the floating gate
105
is formed. And, the minimum design sizes must be used in each of those lithographic processes. Increasing the number of lithographic processes such way will also increase the number of manufacturing processes and result in an increase in the cost of forming masks. The minimum design sizes must also be used for forming those masks. A high performance lithographic apparatus is thus required to form those masks at the minimum design sizes, which will further increase the facility cost.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a non-volatile semiconductor memory device that can speed up both writing and erasing performances without increasing the memory cell area and can be manufactured at a low cost.
A semiconductor memory device of the present invention comprises, a semiconductor substrate, a first diffusion region formed in the semiconductor substrate, a second diffusion region formed in the semiconductor substrate, the second diffusion region apart from the first diffusion region, an insulating film formed between the first diffusion region and the second diffusion region on the semiconductor substrate; and a gate film formed on the insulating film, the gate film having a projection portion on the end portion thereof.
A semiconductor memory device of the other present invention comprises, a semiconductor substrate; a first diffusion region and a second diffusion region formed selectively on the semiconductor substrate, a first insulating film formed between the first diffusion region and the second diffusion region on the semiconductor substrate, a second insulating film formed between the first insulating film and the first diffusion region on the semiconductor substrate, a third insulating film formed between the first insulating film and the second diffusion region on the semiconductor substrate, the first insulating film having a thickness which is thicker than the thickness of each of the second and third insulating film; and a gate film formed on the first insulating film, the gate film have a projection portion protruded from the end portion thereof.
A method for manufacturing a semiconductor memory device of the present invention comprises:
forming a first insulating film selectively on a substrate;
forming a first conductor film on the first insulating film;
forming a second insulating film on the first conductor film;
forming a third insulating film on the second insulating film;
forming a fourth insulating film on a surface of the substrate and on a side surface of the first conductor;
forming a second conductor film on the fourth insulating film so that the fourth insulating film is sandwiched between the first conductor film and the second conductor film, and on a side surface of the second insulating film;
removing the second and the third
Eckert George
NEC Electronics Corporation
Scully Scott Murphy & Presser
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