Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2000-12-21
2002-07-16
Tran, M. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185240
Reexamination Certificate
active
06421277
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device which erases data of memory cells all at once, and particularly, for an NOR type flash memory, a non-volatile semiconductor memory device in which data of the memory cells is over-erased so as to give rise to problems.
2. Description of Related Art Including Information Disclosed Under 37 CFR 1.97 and 37 CFR 1.98
Recently, a flash memory is mainly used as a non-volatile semiconductor memory device in which data can be electrically written into and erased from the memory cell. The flash memory can erase data of the memory cells all at once for each block (which is also called a “sector”) composed of memory cells of all or a part of a memory cell array.
In a flash memory, electrons are injected into a floating gate of the memory cell in order to write into the memory cell or are extracted from the floating gate of the memory cell in order to erase from the memory cell. Since a threshold voltage of the memory cell is varied depending on the amount of electric charge accumulated in the floating gate, using this property, when electrons are injected into the floating gate and the threshold voltage reaches a high level (writing state) for example, this condition corresponds to a logic value of “0”. On the other hand, when electrons are extracted from the floating gate and the threshold voltage reaches a low level (erasing state) for example, this condition corresponds to a logic value of “1”.
However, the erasing speed depends on each memory cell because of the variation in the quality such as the thickness of the oxide film of the transistors composing the memory cells, or minor defects. Even if the data of the memory cells is erased using the same method, the threshold voltages of every memory cell are not uniform and the threshold voltage has a predetermined distribution in view of the memory cells as a whole. If batch erasing is performed until reaching the threshold voltage for the memory cells having a slow erasing speed, the batch erasing will be excessively performed for the memory cells having a fast erasing speed. A memory cell in which data is over-erased is called “a memory cell having deep depletion” or “a memory cell having a depletion defect”. Such memory cells in which data is over-erased generate various problems; therefore, it is required that the presence of these memory cells be completely eliminated.
A flash memory utilizing a countermeasure for memory cells having deep depletion is disclosed in, for example, Japanese Unexamined Patent Application No. Hei 8-106793 (hereinafter, referred to as JP 8-106793). In this application, erasing the data of the memory cell in an erasure block is performed as follows. A memory cell having a low threshold voltage, logic value “1”, is detected and is written until reaching a high threshold voltage, logic value “0”, so that every memory cell in the erasure block has a high threshold voltage, logic value “0”. Next, the data of all memory cells in the erasure block is erased all at once so that each memory cell has a logic value “1”. The data of the memory cells is erased so that the upper limit of the threshold voltage of each memory cell is the predetermined “erase verify voltage”.
As described above, when the batch erasing is performed, memory cells having deep depletion are generated in which the threshold voltage is negative due to the variations in the erasing speeds of each memory cell. The voltage of a word line applied to a control gate of the memory cell is set to “0 V”, and memory cells having deep depletion are detected and rewritten so as not to be in depletion. Because it is not known which memory cells connected to a digit line (which is also referred to a bit line, a data line, or the like) have deep depletion, the rewrite is performed for each digit line and not for each memory cell.
Therefore, shallow writing is performed in every memory cell connected to the digit line, verifying is performed to detect whether depletion is not in the digit line, and shallow rewriting is repeated until the data of memory cells in the digit line having deep depletion is completely erased. The voltage of the word line is set to “1.2 V” and rewriting and verifying are performed for each memory cell, in the same way that “0 V” is applied to the word line, in order to rewrite memory cells having latent deep depletion.
However, in the flash memory disclosed in the above-mentioned document JP 8-106793, the following problems arises.
FIG. 8
shows graphs explaining this problem, and shows the threshold voltage distribution for memory cells as a whole in the erasure block. The X-axes show the number of memory cells N for each threshold voltage, and the Y-axes show the threshold voltages Vtm of the memory cells. The graph on the left in
FIG. 8
shows the actual distributions of the threshold voltage. The distribution indicated by a reference letter D
1
shows memory cells having deep depletion, and the distribution indicated by a reference letter D
2
shows normally erased memory cells having no depletion.
Furthermore, the graph in the center of
FIG. 8
shows the apparent distributions of the threshold voltage. The distribution of normally erased memory cells indicated by a reference letter D
3
seems to be at lower position than distribution D
2
shown in the graph on the left. This is caused by the existence of memory cells having deep depletion shown in distribution D
1
. The will be explained as follows.
FIG. 9
is a partial diagrammatic view of a flash memory. A digit line
100
is one of the digit lines composing the memory cell array. A sense amplifier
101
senses a memory data of the memory cell connected to digit line
100
by comparing an amount of electric current of a current Id passing through digit line
100
with an amount of electric current of a predetermined reference electric current.
Furthermore, each of the memory cells
102
to
104
is a part of the memory cells connected to the digit line
100
. Word lines
105
to
107
are signal lines for selecting these memory cells
102
to
104
. Electric currents Ic
1
to Ic
3
are currents passed between the drain sources of memory cells
102
to
104
, respectively. Memory cells
102
and
103
are in a writing state and memory cell
104
is a memory cell having deep depletion. To determine the threshold voltage of memory cell
102
, a predetermined voltage is applied to word line
105
, and word lines
106
and
107
and other word lines (not shown) are set to “0V”.
In contrast, if memory cell
104
is not a memory cell having deep depletion, as long as the above predetermined voltage applied to word line
105
does not reach the threshold voltage of memory cell
102
, memory cell
102
will remain OFF and the amount of electric current Ic
1
is approximately “0”. Since electric current is not applied to word lines other than word line
105
, the amounts of electric current Ic
2
and Ic
3
are approximately “0”. Therefore, the amount of electric current Id becomes approximately “0”. On the other hand, when the predetermined voltage applied to word line
105
is equal to or greater than the threshold voltage of memory cell
102
, memory cell
102
turns ON. Subsequently, electric current Ic
1
, depending on the characteristics of memory cell
102
, flows, and electric current Id equals electric current Ic
1
since the amounts of electric currents Ic
2
and Ic
3
are “0”. Therefore, sense amplifier
101
senses the amount of electric current Id to determine whether the threshold voltage of memory cell
102
is equal to or greater than the predetermined voltage.
However, if memory cell
104
is a memory cell having deep depletion, for example, when memory cell
102
is read, even if the actual data stored in each memory cell is “0”, an error reading may occur as if the data stored in the memory cell was “1”. Since the threshold voltage of memory cell
104
having deep depletion is less than “0 V”, a considerable amount of electric current Ic
Hutchins, Wheeler & Dittmar
NEC Corporation
Tran M.
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