Non-volatile semiconductor memory device

Details Non-volatile semiconductor memory device Non-volatile semiconductor memory device

2000-09-27

2002-07-16

Nelms, David (Department: 2818)

Static information storage and retrieval

Floating gate

Particular connection

C365S185110, C365S185170

Reexamination Certificate

active

06421272

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a non-volatile semiconductor memory device, in particular, a non-volatile semiconductor memory device that can maintain its data holding characteristics even though the number of writing data is increased.
BACKGROUND OF THE INVENTION
A non-volatile semiconductor memory that can electrically rewrite has been proposed, using a MOS transistor of double-layered structure, which has a floating gate and a control gate. The semiconductor memory writes data by injecting electric charges from a channel through a floating gate via an insulation layer by a tunnel current. The injected electric charge is used as information storage of digital bits. It can read the information out by sensing a conductance change of a MOSFET responsive to the electric charge.
However, if, in the construction of the non-volatile semiconductor memory and by the method thereof, electric charge injection is repeated while increasing the current density in order to write data at a high speed, the abovementioned insulation film is deteriorated to increase the leakage current, and finally the data holding characteristics thereof may be worsened. The problem is described below with reference to FIG.
12
and FIG.
13
.
FIG. 12
shows a memory cell matrix of a prior art non-volatile semiconductor memory and a circuit block of the major parts of the peripheries thereof.
In FIG.
12
(
a
), reference numbers
1
and
1
′ indicate data transfer lines,
6
and
6
′ indicate data selection lines. These lines are disposed in the direction orthogonal to each other. Reference number
3
indicates a memory cell unit, and is provided at the intersections between the data transfer lines
1
,
1
′ and data selection lines
6
,
6
′.
In FIG.
12
(
a
), four memory cell units
3
are connected to each of data transfer lines
1
,
1
′, and two memory cell units are connected to each of data selection lines
6
,
6
′, thereby constituting a 2×4 memory cell unit matrix. Further, a latch
4
or
4
′, which provisionally holds written data is provided at one end of the respective data transfer lines
1
,
1
′.
The latches
4
,
4
′ concurrently act as a sensing amplifier circuit to read out data of the memory cell units
3
. Also, data lines
10
,
10
′ are connected to the latches
4
,
4
′ in order to transmit written and read data to a peripheral circuit and receive the same therefrom. In addition, the latches
4
,
4
′ are both connected to a signal line which establishes timing to latch data. In this structure, memory cell units a
11
, a
12
a
21
, a
22
, connected to one data transfer line such as data transfer line
1
mean memory block.
And, as shown in FIG.
12
(
b
), a clock generation circuit
11
, which adequately executes the timing and output a signal thereof is provided at the signal line
9
and data selection lines
6
,
6
′. Also, hereinafter, in compliance with the practice, the direction along the data selection lines
6
,
6
′ is called a “column”, and the direction along the data transfer line
1
is called a “row”.
In a prior art circuit shown in
FIG. 12
, where data are written in the memory cell units a
11
and b
11
, it is necessary to apply an electric potential to the data transfer lines
1
,
1
′ to which the memory cell units a
11
and b
11
are connected. Therefore, the output voltage of the data latches
4
,
4
′ is adjusted so as to become a voltage value responsive to writing data. At the same time, a program voltage Vpgm that has a larger potential difference than the potential of the data transfer line in which writing is carried out is applied to the data selection line
6
. At this time, the program voltage Vpgm is applied so that a high voltage enough to cause an electric current to flow in the abovementioned insulation film (the gate insulation film of the MOSFET) of a memory element located in the memory cell unit
3
is applied. At this time, the program voltage Vpgm is made pulse-like while having a sufficient duration of time of carrier injection.
In this case, it is requested that data of the memory cell unit a
11
is not erroneously written in a non-selected memory cell unit, for example memory cell unit a
21
, connected to the same data transfer line
1
as that of the memory cell unit a
11
. Therefore, it is necessary that the potential of the data selection line
6
connected to the non-selected memory cell unit a
21
approaches the potential of the data transfer lines
1
,
1
′ further than the abovementioned program voltage Vpgm. Accordingly, it is impossible to write optional data in memory data of a plurality of columns. That is, the number of lines in which data can be written per program pulse is one column.
FIG. 13
shows a flowchart of the non-volatile semiconductor memory, including a verification motion that can carry out writing of data in a plurality of columns, for example, two columns.
A sequence of writing data in memory cell units a
11
, b
11
of the first column is comprised of a step (S1) for loading data to be written in the first column in the latches
4
,
4
′, a step (S2) for applying a program pulse to the data selection line
6
, to which the memory cell units a
11
and b
11
of the first column is connected, a step (S3) for storing the result of judgment of a threshold of the memory cell units from and in which the data of the first column is read and written, into the data latches
4
,
4
′, a step (S4) for judging the result of judgment about whether or not writing is completed in all the memory cell units of the first column, and a step (S5) for re-establishing a program pulse voltage and a pulse width in a case where the result of the judgment in the step S4 is No. Also, hereinafter, the sequence in which only the column differs is expressed with a dash (′) attached.
Therefore, in a case where data are written in a plurality (for example, n columns) of memory cell units, it is necessary to carry out the same sequence as the abovementioned sequence from S1 through S5 “n” times in time series as described in steps S1′ through S5′. In this case, where it is assumed that the times necessary for motions in S1, S2, S3, and S4 are TS1, TS2, TS3 and TS4, the time required to write all the data is at least n×(TS1+TS2+TS3+TS4). Therefore, if the number of columns is increased “n” times, the writing time is accordingly increased “n” times.
Herein, in order to decrease the time required to write all the data, there is a method of decreasing the program time TS2 that takes most time. But, if, with respect to an electric charge required to write, the writing current is increased, low field leakage of the tunnel insulation film is increased further than the writing current is decreased by lengthening the program time (K. Naruke, 1988, IEEE Technical Digest IEDM p.424).
Also, if a silicon oxide film is used as a gate insulation film of the memory element, there arises another problem that a stress leakage current flows to the gate insulation film. When writing, the gate insulation film may receive a larger field stress than 10 MV/cm in order to flow an FN tunnel current to. By receiving the field stress, a leakage current flows at a low field that is, for example, 5 MV/cm or less. The leakage current may be increased further than the value that can be presumed by the FN tunnel current. This is a stress leakage current.
For this reason, in a non-volatile semiconductor memory in which data are repeatedly written and deleted, a leakage current flow since an electric field resulting from electric charge accumulation is applied between a floating gate and a substrate in a state where an electric charge is held, and the electric charge is liable to disappear. In a non-volatile semiconductor memory, it is requested that information is retained and held in a high temperature of at least 85° C. for ten years, it was necessary to prevent the electric charge from disappearing with no powe

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