Non-volatile semiconductor memory device

Details Non-volatile semiconductor memory device Non-volatile semiconductor memory device

1995-09-29

1997-02-04

Monin, Jr., Donald L.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257392, H01L 2702, H01L 2978

Patent

active

056001649

ABSTRACT:
An object of the present invention is to achieve an improved flash memory which enables to simultaneously obtain high performance and reliability even with voltage V.sub.CC of 3.3 V or below. The device includes a memory cell 6, a V.sub.CC type transistor 7 and a V.sub.PP type transistor 8. Memory cell 6 includes a tunnel oxide film 2, a floating gate 3 and a control gate 4. A V.sub.CC type transistor 7 includes a first gate insulating film 9 and a first gate 10. A V.sub.PP type transistor 8 includes a second gate insulating film 11 and a second gate 12. An inequality, t(V.sub.CC)<t(TN)<t(V.sub.PP), is satisfied where t(TN) is the thickness of the tunnel oxide film, t(V.sub.CC) is the thickness of the first gate insulating film, and t(V.sub.PP) is the thickness of the second gate insulating film.

REFERENCES:
patent: 4471373 (1984-09-01), Shimizu et al.
patent: 5194924 (1993-03-01), Komori et al.
patent: 5237188 (1993-08-01), Iwai et al.
"Stress Induced Leakage Current Limiting to Scale Down EEPROM Tunnel Oxide Thickness", by K. Naruke et al., IDEM 88 pp. 424-427 no date.
"Flash EEPROM Cell Scaling Based on Tunnel Oxide Thinning Limitations", by K. Yoshikawa et al., Symposium on VLSI Technology Digest (1991) pp. 79-80 no month.

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