Static information storage and retrieval – Read/write circuit – Differential sensing
Patent
1988-11-18
1990-06-12
Popek, Joseph A.
Static information storage and retrieval
Read/write circuit
Differential sensing
36523003, 365204, G11C 700
Patent
active
049339060
ABSTRACT:
A semiconductor memory device of erasable programmable rear only memory type is disclosed the memory device has a pair of memory cell arrays between which a differential amplifier is provided. Each of the memory cell arrays has a current-to-voltage converter circuit associated therewith. When a memory cell in either one of the pair of memory cell array is selected, a bit line being coupled to the selected memory cell is charged by one current-voltage conversion circuit, while at the same time at least one bit line in the other memory cell array where no memory cell has been selected is charged by the associated current-voltage converter circuit at arrayed different from the bit line coupled to the selected memory cell. A differential amplifier senses and amplifies a potential difference between the charged bit lines to provide a high speed read-out of the memory device.
REFERENCES:
patent: 4503522 (1985-03-01), Etoh et al.
F. Masouka et al., "A 256k Flash EEPROM Using Triple Polysilicon Technology", ISSCC 85, Feb. 14, 1985, Digest of Technical Papers, pp. 168, 169 and 335.
R. Zeman et al., "A 55ns CMOS EEPROM", ISSCC84, Feb. 23, 1984, Digest of Technical Papers, pp. 144-145.
M. Yoshida et al., "An 80ns Address-Data Multiples 1Mb CMOS EPROM", ISSCC, Feb. 25, 1987, Digest of Technical Papers, pp. 70, 71 and 342.
Kobayashi Kazuo
Nakayama Takeshi
Terada Yasushi
Mitsubishi Denki & Kabushiki Kaisha
Popek Joseph A.
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